Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA .
DETAILED ACTION
1. The office acknowledges the receipt of the following and placed of record in the file: Application dated 12/10/24.
2. Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1, 6-8, 13, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Basile et al. U.S. Patent Publication No. 2016/0048184 and Pereira et al. (“Pereira”), U.S. Patent No. 9644593.
Regarding Claims 1, 17 and 20, Basile teaches an apparatus, comprising: at least one memory comprising computer-executable instructions [Para: 0009(software)]; and
one or more processors configured to execute the computer-executable instructions [Para: “non-volatile memory device that contains firmware … to boot multiple central processing units (CPUs)”) and 0013(firmware 114can be executed by the CPUs 102)] and cause the apparatus to:
a first group of processing cores [Para; 0009 (at least two of the “plurality of CPUs”)], wherein the first group of processing cores shares a first voltage supply rail with at least a second group of processing cores [ Para: 0014( remaining CPUs of the plurality of agents 202 which shares power over bus 208 as described “bus arbiter 218 can be can grant bus access to each CPU 102 as such CPU is powered on” in para 0018)]. Basile also teaches decouple memory of the first group of processing cores from the first voltage supply rail, when a state indicates it is ready to transition [Para: 0018(bus 216 selectively couples the agents 202 to the non-volatile memory … based on state of the power control state machines 214”)].
Basile does not disclose expressly select a first performance state (p-state) for a processor and decouple memory of the processing core from a voltage supply rail, when at least one condition involving the first p-state is met.
In the same field of endeavor (e.g., power control in a circuit including processor and memory device), Pereira teaches select a first performance state (p-state) for a processor (at 510 checking “whether Vsupply is smaller than a selected threshold (Vth)” a crank event suggests that a performance level at a threshold voltage is selected) and decouple a memory of the processing core from a voltage supply rail, when at least one condition involving the first p-state is met [col-5 lines: 20-45 (‘in response to the crank event, RAM 103 is isolated by opening switching circuit 304 … Ram is isolated by opening switching circuit 304 … disabling regulator 302”)].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Basile’s teachings of decouple memory of the first group of processing cores from the first voltage supply rail, when a state indicates it is ready to transition with Pereira’s teachings of select a first performance state (p-state) for a processor and decouple memory of the processing core from a voltage supply rail, when at least one condition involving the first p-state is met would allow Basile to dynamically connect/disconnecting the memory with a power rail based on performance in order to save power for battery.
Regarding Claim 6, Pereira teaches wherein the at least one condition involves an operating voltage associated with the first p-state [col-3 lines: 33-50 (“First regulator 302 is configured to output a first voltage value “VDD_LV_FP” and second regulator 303 is configured to output a second voltage value “VDD_LV_LP.” Second regulator 303 is also configured to receive a “REG_LP_EN” signal, …”) and col-5 lines: 20-30 and Fig-3].
4. Claim(s) 2-5 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Basile and Pereira as above (“Basile-Pereira”) and Kachare et al. (“Kachare”), U.S. Patent Pub No. 2020/0183583.
Regarding Claims 2 and 18, Basile-Pereira teaches wherein the decoupling involves coupling the memory of the first group of processing cores to a second voltage supply rail when the at least one condition is met [Fig-3(decupling from voltage rail VDD_LV_FP 304 to voltage rail VDD_LV_LP 303)]. Basile-Pereira does not disclose expressly decupling involves a multiplexor.
In the same field of endeavor (e.g., data processing circuit involving storage), Cachare teaches decupling involves a multiplexor (mux-506) [Para: 0067, 0071 and Fig-5A].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Basile-Pereira’s teachings of decoupling involves coupling the memory of the first group of processing cores to a second voltage supply rail when the at least one condition is met with Kachare’s teachings of decupling involves a multiplexor would allow Basile-Pereira to switch power rail in swift manner in order to have an efficient system.
Regarding Claims 3 and 19, Basile-Pereira teaches a control signal generated by first with the first group of processing cores a set forth above.
Kachare teaches wherein a multiplexor comprises an adaptive power multiplexor (APM) responsive to an APM control logic associated with a signal [Para: 0067(as multiplexer 506 selects)].
Regarding Claim 4-5, since they are directly related to Claims 1 and 3 (according to the Examiner’s interpretation), the supporting rationale of the rejection to Claims 1 and 3 applies equally as well to Claims 4-5.
5. Claim(s) 7-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over “Basile-Pereira” as state above and Tripathi et al. (“Tripathi”), US 20160291625.
Regarding Claim 7, Basile-Pereira teaches all limitations of claim 7 as described rejecting Claim 1 above. Basile-Pereira does not disclose expressly wherein the at least one condition is considered met when the operating voltage associated with the first p-state exceeds a reference voltage.
In the same field of endeavor (e.g., power control in a circuit based on threshold voltage), Tripathi teaches wherein one condition is considered met when the operating voltage associated with a p-state exceeds a reference voltage [Abstract, Para: 0006(“If the supply voltage subsequently rises to a level above the second threshold” where “the second voltage threshold being greater than the first … operation in a particular performance state by a corresponding functional circuit”)] .
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Basile-Pereira’s teachings of decouple memory of the first group of processing cores from the first voltage supply rail, when a state indicates it is ready to transition with Tripathi’s teachings of one condition is considered met when the operating voltage associated with a p-state exceeds a reference voltage for a processor would allow Basile-Pereira to allow operating in higher performance and increased processing throughput for a particular IC [Tripathi, Para: 0005].
Regarding Claim 8, Tripathi teaches wherein the reference voltage corresponds to a maximum operating voltage associated with the second group of processing cores [Para: 0004].
Regarding Claims 9-11, since they are directly related to Claims 1, 7 and 8 (according to the Examiner’s interpretation), the supporting rationale of the rejection to Claims 1, 7 and 8 applies equally as well to Claims 9-11.
Regarding Claims 12-15, Claims recites various aspects of selecting first and/or second processor group with respective power rail with well known in the industry such as cores are associated with different electrical margin adjust (EMA) band, adjusting memory operations based on EMA band via dynamic performance setting bits based on first and second voltage rails reference voltage and one of ordinary skill in the art would utilize above mentioned obvious variations based on user requirement in order to have commercial success.
6. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Basile-Pereira and Tripathi as applied to claim 9 above (hereinafter, “BPT”) and Prasad et al. (“Prasad”), U.S. Patent Pub No. 2023/0062482.
Regarding Claim 16, BPT teaches all limitations of claim 16 as described rejecting Claim 9 above. BPT does not disclose expressly the memory of the first group of processing cores comprises high current (HC) bitcells and memory of the second group of processing cores comprises high density (HD) bitcells.
In the same field of endeavor (e.g., OAM implementation in data routing network), Prasad teaches a memory of processing cores comprises high current (HC) bitcells and a memory of a second processing cores comprises high density (HD) bitcells [Para: 0127(“two types of SRAM bitcells that may be utilized include: high density (HD) or high current (HC)” and 0128(“high density (HD) memory instead of a “flipped” high current (HC) memory …”)]
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify BPT’s teachings of first group of processing cores and second group of processing cores having respective memories with Prasad’s teachings of a memory of processing cores comprises high current (HC) bitcells and a memory of a second processing cores comprises high density (HD) bitcells would allow BPT to achieve “power, performance, area, cost efficiency” [Parasad, 0003] in a circuit design.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED H REHMAN whose telephone number is (571)272-1412. The examiner can normally be reached 8.00 - 5.00.
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/MOHAMMED H REHMAN/Primary Examiner, Art Unit 2176
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