DETAILED ACTION
1. This Office Action is responsive to claims filed for App. 18/976,054 on April 28, 2026. Claims 1-16 are pending.
America Invents Act
2. The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 28, 2026 has been entered.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887,225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937,214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
5. Claims 1-16 provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1 of copending Application No. 18/981,380 ( Herein after referred to as 380 ). Although the conflicting claims are not identical, they are not patentably distinct from each other because the claims of the current application are included in 380.
This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented.
Application 380 Claim 1
Current Application 18/976,054 Claim 1
A micro-LED display apparatus, comprising: a timing controller configured to output image data; a display panel including a plurality of pixel arrays that are connected to a data line; and a data driver configured to generate a data voltage based on the image data and apply the data voltage to the data line,
A micro LED display apparatus, comprising:
a timing controller configured to output image data; a display panel on which a pixel array connected to a data line is disposed; and
a data driver configured to generate a data voltage based on the image data and to apply the data voltage to the data line,
wherein a pixel array of the plurality of pixel arrays comprises a gate in array (GIA) circuit that provides a scan signal to a subpixel of the pixel array, and wherein the GIA circuit comprises:
wherein the pixel array comprises a gate in active (GIA) circuit configured to provide a scan signal to a subpixel in the pixel array, and
a first transistor including a gate electrode connected to a QB node of the GIA circuit, a source electrode that receives a gate high voltage, and a drain electrode that outputs an N-th carry signal;
a first transistor including a gate electrode connected to an N-th scan signal, a source electrode connected to a gate high voltage, and a drain electrode connected to a B node;
a second transistor including a gate electrode connected to a Q node of the GIA circuit, a source electrode that outputs the N-th carry signal, and a drain electrode that receives an N-th carry clock signal.
a second transistor including a gate electrode connected to the N-th scan signal, a source electrode connected to the gate high voltage, and a drain electrode connected to an F node.
a third transistor including a gate electrode connected to the same QB node as the gate electrode of the first transistor, a source electrode that receives the gate high voltage, and a drain electrode that outputs an N-th scan signal; and
a third transistor including a gate electrode connected to the drain electrode of the first transistor; and
a fourth transistor including a gate electrode connected to the same Q node as the gate electrode of the second transistor, a source electrode that outputs the N-th scan signal, and a drain electrode that receives an N-th clock signal.
a fourth transistor including a gate electrode connected to the drain electrode of the second transistor, and
wherein the gate electrode of the first transistor and the gate electrode of the second transistor are connected to the same N-th scan signal, and the source electrode of the first transistor and the source electrode of the second transistor are connected to the same gate high voltage.
As can be seen from above, Claim 1 of Application 380 includes most of the limitations of Claim 1 of the current application, except that Claim 1 of this application has different connections for the first and second transistor. However, the concept of the GIA transistors is common and the minor differences are not patentably distinct.
To further expand on the new claim amendments, Examiner feels these are an attempt to distinguish the claim set from the co-pending Application ‘380. However, the aspects of the third transistor and fourth transistor are present in both applications and the minor differences in connections (such as what electrodes of the first and second transistor the third and fourth transistors are connected to) are not a patentable distinction. The key point here is that both claim sets recites aspects of the third and fourth transistors.
Furthermore, to repeat earlier points and for aspects of the first and second transistor, please note:
“a first transistor including a gate electrode connected to an N-th scan signal”
“a second transistor including a gate electrode connected to the N-th scan signal”
Furthermore, the source electrodes of the first and second electrode being connected to the same gate high voltage were also redundantly claimed:
“a source electrode connected to a gate high voltage”
“a source electrode connected to the gate high voltage”
As a result, Examiner does not feel these elements add patentable distinctions to the claim and because of the redundancy, the original reasoning of obviousness-type double patenting is still applicable.
Independent claim 9 of the current application is obvious in its limitations to claim 8 of 380 and is rejected as well on the ground of provisional nonstatutory obviousness-type double patenting.
Dependent claims 2-8 and 10-16 of the current application are obvious in their limitations to claims 2-7 and 9-14 of application 380 and are rejected as well on the ground of provisional nonstatutory obviousness-type double patenting.
Response to Arguments
6. Applicant’s arguments considered, but are respectfully not persuasive.
Please note the updated rejection in the obviousness-type double patenting rejection. Examiner’s reasoning is provided there, mostly focusing on the redundancy of the newly added limitations, focusing on the third and fourth transistors. These limitations were both added to their respective claim sets, in both applications, in the most recent amendments. The key point here is that both claim sets focus on the third and fourth transistor.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS P JOSEPH whose telephone number is (571)270-1459. The examiner can normally be reached Monday - Friday 5:30 - 3:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621
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