DETAILED ACTION
The instant action is in response to application 10 December 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Priority
Acknowledgment is made of applicant's claim for priority to 10 December 2024.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 14, 18 are rejected under 35 U.S.C. 102(a)(1) and 102 (a)(2) as being anticipated by Zhang (US 20160248328).
As to claim 1, Zhang discloses (Fig. 6) an apparatus comprising: a first control path (622) configured to provide a dc load line setting; and a second control path (624) configured to provide an ac load line setting, wherein: the dc load line setting is configured to determine a load and output voltage relationship during steady state operating conditions; the ac load line setting is configured to provide a fast transient response during transient operating conditions (¶70“The low pass filter 622b blocks the higher frequency component ITH.sub.AC of the transient control signal ITH and allows the lower frequency component ITH.sub.DC of the transient control signal ITH to pass through. The lower frequency component ITH.sub.DC is provided to the non-inverting terminal of the comparator 622c and compared with the sensed current i.sub.LDC in the inductor 616c (low frequency inductor current) to generate the PWM signal for power FETs 616a and 616b..”); and the first control path is independent from the second control path (the tow signals provide separate transient and steady state control signals. It is also noted that Zhang mentions that the AC signal may generate zero current in steady state in ¶14).
As to claim 2, Zhang discloses wherein: the first control path is a dc load line control path, and the first control path is a slow control path; and the second control path is an ac load line control path, and wherein the second control path is fast control path (see Fig. 6).
As to claim 3, Zhang discloses wherein: the first control path comprises a dc load line control unit (622a) and an integrator time constant control unit connected in cascade (622b) ; and the second control path comprises an ac load line control unit (622b) and an ac gain control unit (624b) connected in cascade.
As to claim 14, Zhang discloses A method comprising: configuring a plurality of power stages to provide power to a load, wherein the plurality of power stages is connected in parallel between an input voltage bus and an output voltage bus; configuring a first control path to provide a dc load line setting for the plurality of power stages, wherein the dc load line setting is configured to determine a load and output voltage relationship during steady state operating conditions; and configuring a second control path to provide an ac load line setting for the plurality of power stages, wherein the ac load line setting is configured to provide a fast transient response during transient operating conditions (this is similar to claim 1, with the main difference being the plurality of power stages claim. The transient stage 618 and steady state stage 616 read on this limitation and are also shown in Fig. 6).
As to claim 18, Zhang discloses A power conversion system comprising: a plurality of power stages connected in parallel between an input voltage bus and an output voltage bus; and a controller comprising a first control path configured to provide a dc load line setting and a second control path configured to provide an ac load line setting, wherein: the dc load line setting is configured to determine a load and output voltage relationship during steady state operating conditions; the ac load line setting is configured to provide a fast transient response during transient operating conditions; and the first control path is independent from the second control path (see explanations of claim 14 above).
Allowable Subject Matter
Claims 4-13, 15-17, 19-20 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 4, the prior art fails to disclose: “further comprising: an averaging circuit comprising a first amplifier configured to receive a plurality of current sense signals and generate an average current signal fed into the dc load line control unit and the ac load line control unit; and a first summing circuit configured to receive a reference signal, a positive output voltage signal, a negative output voltage signal and a load line control signal, and generate a droop signal fed into the dc load line control unit and the ac load line control unit.” in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 5, the prior art fails to disclose: “further comprising: a second summing circuit configured to receive an output of the integrator time constant control unit and an output of the ac gain control unit, and generate a control signal; a PWM comparator configured to receive the control signal, a predetermined reference signal and a ramp signal, and generate a PWM signal; and a phase control logic unit configured to receive the PWM signal, and generate a plurality of gate drive signals for a plurality of power stages of a multiphase power conversion system.” in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 6, the prior art fails to disclose " wherein: the dc load line control unit comprises a first resistor, a second resistor, a third resistor and a second amplifier, and wherein: the first resistor and the second resistor are connected in series between a first node and a second node, where an average current signal is tapped at the first node, and a droop signal is tapped at the second node; an inverting input of the second amplifier is connected to a common node of the first resistor and the second resistor; the third resistor is connected between the inverting input and an output of the second amplifier; and a non-inverting input of the second amplifier is connected to a reference.” in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 10, the prior art fails to disclose wherein: the ac load line control unit comprises a fifth resistor, a sixth resistor, a seventh resistor and a fourth amplifier, and wherein: the fifth resistor and the sixth resistor are connected in series between a first node and a second node, where an average current signal is tapped at the first node, and a droop signal is tapped at the second node; an inverting input of the fourth amplifier is connected to a common node of the fifth resistor and the sixth resistor; the seventh resistor is connected between the inverting input and an output of the fourth amplifier; and a non-inverting input of the fourth amplifier is connected to a reference..” in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 15, the prior art fails to disclose " wherein: the first control path comprises a dc load line control unit and an integrator time constant control unit connected in cascade between an averaging circuit and a first input of a second summing circuit; and the second control path comprises an ac load line control unit and an ac gain control unit connected in cascade between a first summing circuit and a second input of the second summing circuit, and wherein: the averaging circuit comprises a first amplifier configured to receive a plurality of current sense signals and generate an average current signal fed into the dc load line control unit and the ac load line control unit; and the first summing circuit is configured to receive a reference signal, a positive output voltage signal, a negative output voltage signal and a load line control signal, and generate a droop signal fed into the dc load line control unit and the ac load line control unit.” in combination with the additionally claimed features, as are claimed by the Applicant
As to claim 19, the prior art fails to disclose " further comprising: an averaging circuit comprising a first amplifier; a first summing circuit; a second summing circuit configured to receive an output of an integrator time constant control unit and an output of an ac gain control unit, and generate a control signal; a PWM comparator configured to receive the control signal, a predetermined reference signal and a ramp signal, and generate a PWM signal; and a phase control logic unit configured to receive the PWM signal, and generate a plurality of gate drive signals for the plurality of power stages, wherein: the first control path comprises a dc load line control unit and the integrator time constant control unit connected in cascade; and the second control path comprises an ac load line control unit and the ac gain control unit connected in cascade, and wherein: the averaging circuit is configured to receive a plurality of current sense signals and generate an average current signal fed into the dc load line control unit and the ac load line control unit; and the first summing circuit is configured to receive a reference signal, a positive output voltage signal, a negative output voltage signal and a load line control signal, and generate a droop signal fed into the dc load line control unit and the ac load line control unit.” in combination with the additionally claimed features, as are claimed by the Applicant
Please note: while objected or allowed claims have been indicated, only the presented claims have been examined for compliance with form and 35 USC 112 consideration. As a reminder, claims that are dependent upon objected claims still require examination for form and 35 USC 112 issues even if they overcome 35 USC 102 and 103 rejections. Similarly, amendments incorporating allowable subject matter into independent claims requires reconsideration for dependent claim form and any possible 35 USC 112 issues that arise through amendments even if the 35 USC 102 and 103 rejections are overcome. As such, applicant is advised that while examiner can enter previously allowed claims or previously objected claims rewritten into independent form after final rejection, any other claims may not be entered.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached on 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M NOVAK/ Primary Examiner, Art Unit 2839
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