DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 and 15-21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 11,176,874 B2) in view of Li et al. (US 2015/0077446 A1).
As to claim 1, Kim teaches a display apparatus, comprising:
a pixel array, having a plurality of self-luminous pixel circuits arranged in an array, wherein each of these self-luminous pixel circuits has an emission element (see at least fig. 1: pixel unit 100, emission element EL, col. 5 lines 17-38 “a display device DD includes a pixel unit 100…. the pixel unit 100 may include a plurality of pixels PX[i, j] may include p rows (p being a natural number of 1 or more) and q columns (q being a natural number of 1 or more)”, col. 8 lines 45-47 “the pixel PX[i, j] includes .. an emission element EL.”);
a timing controller, receiving display data to provide pixel voltage data, at least two scan start signals, and an emission start signal in a single frame period (see at least fig. 1: timing controller 200 receives RGB data, scan signals SCS1, SCS2.. , emission control signal ECS; col. 5 line 53 – col. 6 line 10 “The first scan control signal SCS1 may include a first scan start signal.. . The second scan control signal SCS2 may include a second scan start signal .. The emission control signal ECS may include an emission start signal”; col. 6 line 58 – col. 7 line 2 “The timing controller 200 may receive input image data .., may generate image data mRGB, and may supply the image data mRGB to the data driver 500.”; col. 10 lines 55-60 “the pixel PX[i, j] according to FIG. 2 operates during a first frame period 1frame, waveforms of the emission signal supplied through the emission control line EL[i] and the first to fourth scan signals supplied”);
a gate driver, receiving the at least two scan start signals and coupled to these self-luminous pixel circuits, and sequentially activate these self-luminous pixel circuits row by row (see at least col. 5 lines 22 – 38 “The pixels PX[i, j] disposed in a same row (hereinafter, may be referred to as a mixture of horizontal lines) include a same first scan line, a same second scan line, a same third scan line, and a same fourth scan line, and a same emission control line.”; col. 7 lines 2 – 20 “The first scan driver 300 may receive the first scan control signal SCS1… and may sequentially supply first scan signals to the first scan lines SL1[1]… SL1[p] .. while shifting the first scan start signal by a horizontal period 1H .. .. The second scan driver 310 may receive the second scan control signal SCS2 .. and may sequentially supply second scan signals to the second scan lines SL2[1], . . . , SL2[i], . . . , and SL2[p] .. while shifting the second scan start signal by a horizontal period 1H”);
a source driver, receiving the pixel voltage data to provide a plurality of pixel voltages corresponding to these self-luminous pixel circuits (see at least col. 7 lines 50-55 “The data driver 500 may receive .. the image data mRGB from the timing controller 200. The data driver 500 may supply data signals, such as data voltages, corresponding to the image data mRGB into the data lines DL[1], DL[2], . . . , DL[j], . . . , and DL[q].”; col. 8 lines 55-61 “The first transistor T1 may .. supply the data signal, such as a data voltage, to the second node N2 through the data line DL[j].”);
wherein each of these self-luminous pixel circuits determines a driving current flowing through the emission element based on the received pixel voltage (see at least col. 8 lines 48-54 “The driving transistor TD may be turned on by a voltage applied to the first node N1 to generate a driving current and to supply the generated driving current to the emission element EL”; col. 9 lines 38-44 “The storage capacitor Cst may .. store a voltage corresponding to a data signal”; col. 11 lines 53-62 “the driving transistor TD may generate a driving current corresponding to the differential voltage … , and the emission element EL may emit light with a luminance corresponding to the driving current.”);
an emission driving circuit, receiving the emission start signal to provide a plurality of emission signals to these self-luminous pixel circuits and determine a plurality of light-emitting times of these self-luminous pixel circuits (see at least col. 5 lines 45-52 “the emission control signal ECS may be supplied to the emission driver 400”; col. 6 lines 6-10 “The emission control signal ECS may include an emission start signal … for controlling first timing of the emission signal.”; col. 7 lines 39-50 “The emission driver 400 may receive the emission control signal ECS .. and may sequentially supply emission signals to the emission control lines EL[1], . . . , EL[i], . . . , and EL[p] based on the emission control signal ECS. For example, the emission driver 400 may generate light emission signals while shifting the light emission start signal by a horizontal period 1H”).
Kim does not explicitly teach to divide the single frame period into a plurality of sub-frame periods, wherein in response to brightness of each self-luminous pixel circuit in the single frame period is lower than a grayscale threshold, the driving current of each self-luminous pixel circuit in an entire first sub-frame period of the plurality of sub-frame periods is 0, and the driving current of each self-luminous pixel circuit in a second sub-frame period, different from the first sub-frame period, of the plurality of sub-frame periods is greater than 0, and wherein in response to the brightness of each self-luminous pixel circuit in the single frame period is greater than or equal to the grayscale threshold, the driving current of each self-luminous pixel circuit in the first sub-frame period and the second sub-frame period is greater than 0.
Li teaches dividing a single frame period into a plurality of sub-frame periods (see at least [0040] “one frame is divided into two sub-frame time periods T1 and T2. .. The operation timing of the sub-frame periods may be controlled by timing control signals supplied to the timing I/F 342”; [0042] “the source driver 110 supplies the data line DL with a data line voltage”; and [0043] “The gamma-corrected values are output from the DAC 322 to the data lines DL and used as the drive signals for the pixels 104”), and
sequentially activate these self- luminous pixel circuits row by row in each of these sub-frame periods (see at least [0028] “The gate driver 108, under control of the controller 112, operates on address or select lines SEL[i], SEL[i+1], and so forth, one for each row of pixels 104”; [0030] “In row-by-row programming, a row of pixels is programmed and then driven before the next row of pixels is programmed and driven”; [0060] “the strobe signal 646a for the first row produces a pulse 652 to select the row. .. After a sub-frame time period, the programming voltage select signals 642 are selected to send a set of high grayscale range programming voltages 654 to the first row.”; [0061] “As is shown by FIG. 14A, this process is repeated for each of the rows .. Each row is therefore strobed twice”),
wherein in response to brightness of each self-luminous pixel circuit in the single frame period is lower than a grayscale threshold, the driving current of each self-luminous pixel circuit in an entire first sub-frame period of the plurality of sub-frame periods is 0, and the driving current of each self-luminous pixel circuit in a second sub-frame period, different from the first sub-frame period, of the plurality of sub-frame periods is greater than 0 (see at least [0029] “brightness (gray level)”; [0030] “brightness (gray level)”; [0045] “if the raw grayscale value of a pixel is greater than or equal to a reference value D(ref), that data is considered as the high grayscale range HG. If the raw grayscale value is smaller than the reference value D(ref), that data is considered as the low grayscale range LG”; [0069] “the raw input grayscale values are converted to two different sub-frame grayscale values for two different sub-frames SF1 and SF2 of each frame F, so that the current levels are controlled”; [0070] “those values are converted to increased values sf1_gsv for the first sub-frame SF1, and the grayscale value sf2_gsv for the second sub-frame SF2 is maintained at zero. .., the second sub-frame value remains at zero (at relaxation) until the first sub-frame value sf1_gsv reaches a preset threshold value sf1_max, ... Thus, up to this point no drive current is supplied to the pixel during the second sub-frame SF2 and so that the pixel remains black (at relaxation) during the second sub-frame SF2. .. the first sub-frame value sf1_gsv from the LUT is greater than the input value” – note Li’s SF2 corresponds to the claimed first sub-frame period and Li’s SF1 corresponds to the claimed second sub-frame period), and
wherein in response to the brightness of each self-luminous pixel circuit in the single frame period is greater than or equal to the grayscale threshold, the driving current of each self-luminous pixel circuit in the first sub-frame period and the second sub-frame period is greater than 0 (see at least [0071] “after the threshold grayscale value sf1_max is reached, the first sub-frame grayscale value sf1_gsv remains at that maximum value as the input value continues to increase, while the second sub-frame grayscale value sf2_gsv begins to increase from zero. .. , the value of sf2_gsv continues to increase while the first sub-frame value sf1_gsv is decreased”; [0075] “When the input grayscale value reaches 96, the LUT begins to increase the value of sf2_gsv and maintains the value of sf1_gsv at 255” – note once the threshold is reached, both sub-frame grayscale values are greater than zero, corresponding to driving current being greater than zero in both sub-frame periods.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim to employ Li’s sub-frame driving technique because Li teaches dividing a frame into multiple sub-frame periods and controlling current levels in the sub-frame periods according to grayscale threshold values to enhance compensation and provide relaxation intervals that extend display lifetime (see at least [0069]-[0075]). One of ordinary skill in the art would have recognized that applying Li’s known threshold-based sub-frame current control to Kim’s display architecture would predictably provide grayscale-dependent emission control, improved compensation performance, and reduced pixel degradation while utilizing Kim’s existing timing controller, scan drivers, source driver, and emission driver architecture. Further rationale to support a conclusion of obviousness is that all the claimed elements were known in the prior art, and one of ordinary skill in the art could have combined the elements as claimed using known methods to yield predictable results.
As to claim 15, Kim teaches a method of driving pixels of a display apparatus (see at least fig. 1: pixel unit 100), comprising:
a timing controller (see at least fig. 1: timing controller 200);
sequentially activating a plurality of self-luminous pixel circuits row by row via a gate driver (see at least col. 5 lines 22 – 38 “The pixels PX[i, j] disposed in a same row (hereinafter, may be referred to as a mixture of horizontal lines) include a same first scan line, a same second scan line, a same third scan line, and a same fourth scan line, and a same emission control line.”; col. 7 lines 2 – 20 “The first scan driver 300 may receive the first scan control signal SCS1… and may sequentially supply first scan signals to the first scan lines SL1[1]… SL1[p] .. while shifting the first scan start signal by a horizontal period 1H .. .. The second scan driver 310 may receive the second scan control signal SCS2 .. and may sequentially supply second scan signals to the second scan lines SL2[1], . . . , SL2[i], . . . , and SL2[p] .. while shifting the second scan start signal by a horizontal period 1H”),
wherein each of the self-luminous pixel circuits has an emission element (see at least fig. 1: pixel unit 100, emission element EL, col. 8 lines 45-47 “the pixel PX[i, j] includes .. an emission element EL.”);
providing a plurality of pixel voltages corresponding to the self-luminous pixel circuits based on display data via a source driver (see at least col. 7 lines 50-55 “The data driver 500 may receive .. the image data mRGB from the timing controller 200. The data driver 500 may supply data signals, such as data voltages, corresponding to the image data mRGB into the data lines DL[1], DL[2], . . . , DL[j], . . . , and DL[q].”; col. 8 lines 55-61 “The first transistor T1 may .. supply the data signal, such as a data voltage, to the second node N2 through the data line DL[j].”),
wherein each of the self-luminous pixel circuits determines a driving current flowing through the emission element based on the received pixel voltage (see at least col. 8 lines 48-54 “The driving transistor TD may be turned on by a voltage applied to the first node N1 to generate a driving current and to supply the generated driving current to the emission element EL”; col. 9 lines 38-44 “The storage capacitor Cst may .. store a voltage corresponding to a data signal”; col. 11 lines 53-62 “the driving transistor TD may generate a driving current corresponding to the differential voltage … , and the emission element EL may emit light with a luminance corresponding to the driving current.”); and
providing a plurality of emission signals to the self-luminous pixel circuits via an emission driving circuit to determine a plurality of light-emitting times of the self-luminous pixel circuits (see at least col. 5 lines 45-52 “the emission control signal ECS may be supplied to the emission driver 400”; col. 6 lines 6-10 “The emission control signal ECS may include an emission start signal … for controlling first timing of the emission signal.”; col. 7 lines 39-50 “The emission driver 400 may receive the emission control signal ECS .. and may sequentially supply emission signals to the emission control lines EL[1], . . . , EL[i], . . . , and EL[p] based on the emission control signal ECS. For example, the emission driver 400 may generate light emission signals while shifting the light emission start signal by a horizontal period 1H”).
Kim does not explicitly teach to dividing a single frame period into a plurality of sub-frame periods, in response to brightness of each self-luminous pixel circuit in the single frame period is lower than a grayscale threshold, the driving current of each self-luminous pixel circuit in an entire first sub-frame period of the plurality of sub-frame periods is set as 0, and the driving current of each self-luminous pixel circuit in a second sub-frame period, different from the first sub-frame period, of the plurality of sub-frame periods is set as greater than 0; and in response to the brightness of each self-luminous pixel circuit in the single frame period is greater than or equal to the grayscale threshold, the driving current of each self- luminous pixel circuit in the first sub-frame period and the second sub-frame period is set as greater than 0.
Li teaches dividing a single frame period into a plurality of sub-frame periods (see at least [0040] “one frame is divided into two sub-frame time periods T1 and T2. .. The operation timing of the sub-frame periods may be controlled by timing control signals supplied to the timing I/F 342”; [0042] “the source driver 110 supplies the data line DL with a data line voltage”; and [0043] “The gamma-corrected values are output from the DAC 322 to the data lines DL and used as the drive signals for the pixels 104”), and
sequentially activating a plurality of self-luminous pixel circuits row by row in each of the sub-frame periods (see at least [0028] “The gate driver 108, under control of the controller 112, operates on address or select lines SEL[i], SEL[i+1], and so forth, one for each row of pixels 104”; [0030] “In row-by-row programming, a row of pixels is programmed and then driven before the next row of pixels is programmed and driven”; [0060] “the strobe signal 646a for the first row produces a pulse 652 to select the row. .. After a sub-frame time period, the programming voltage select signals 642 are selected to send a set of high grayscale range programming voltages 654 to the first row.”; [0061] “As is shown by FIG. 14A, this process is repeated for each of the rows .. Each row is therefore strobed twice”),
in response to brightness of each self-luminous pixel circuit in the single frame period is lower than a grayscale threshold, the driving current of each self-luminous pixel circuit in an entire first sub-frame period of the plurality of sub-frame periods is set as 0, and the driving current of each self-luminous pixel circuit in a second sub-frame period, different from the first sub-frame period, of the plurality of sub-frame periods is set as greater than 0 (see at least [0029] “brightness (gray level)”; [0030] “brightness (gray level)”; [0045] “if the raw grayscale value of a pixel is greater than or equal to a reference value D(ref), that data is considered as the high grayscale range HG. If the raw grayscale value is smaller than the reference value D(ref), that data is considered as the low grayscale range LG”; [0069] “the raw input grayscale values are converted to two different sub-frame grayscale values for two different sub-frames SF1 and SF2 of each frame F, so that the current levels are controlled”; [0070] “those values are converted to increased values sf1_gsv for the first sub-frame SF1, and the grayscale value sf2_gsv for the second sub-frame SF2 is maintained at zero. .., the second sub-frame value remains at zero (at relaxation) until the first sub-frame value sf1_gsv reaches a preset threshold value sf1_max, ... Thus, up to this point no drive current is supplied to the pixel during the second sub-frame SF2 and so that the pixel remains black (at relaxation) during the second sub-frame SF2. .. the first sub-frame value sf1_gsv from the LUT is greater than the input value” – note Li’s SF2 corresponds to the claimed first sub-frame period and Li’s SF1 corresponds to the claimed second sub-frame period), and
in response to the brightness of each self-luminous pixel circuit in the single frame period is greater than or equal to the grayscale threshold, the driving current of each self- luminous pixel circuit in the first sub-frame period and the second sub-frame period is set as greater than 0 (see at least [0071] “after the threshold grayscale value sf1_max is reached, the first sub-frame grayscale value sf1_gsv remains at that maximum value as the input value continues to increase, while the second sub-frame grayscale value sf2_gsv begins to increase from zero. .. , the value of sf2_gsv continues to increase while the first sub-frame value sf1_gsv is decreased”; [0075] “When the input grayscale value reaches 96, the LUT begins to increase the value of sf2_gsv and maintains the value of sf1_gsv at 255” – note once the threshold is reached, both sub-frame grayscale values are greater than zero, corresponding to driving current being greater than zero in both sub-frame periods.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim to employ Li’s sub-frame driving technique because Li teaches dividing a frame into multiple sub-frame periods and controlling current levels in the sub-frame periods according to grayscale threshold values to enhance compensation and provide relaxation intervals that extend display lifetime (see at least [0069]-[0075]). One of ordinary skill in the art would have recognized that applying Li’s known threshold-based sub-frame current control to Kim’s display architecture would predictably provide grayscale-dependent emission control, improved compensation performance, and reduced pixel degradation while utilizing Kim’s existing timing controller, scan drivers, source driver, and emission driver architecture. Further rationale to support a conclusion of obviousness is that all the claimed elements were known in the prior art, and one of ordinary skill in the art could have combined the elements as claimed using known methods to yield predictable results.
As to claim 2, the combination of Kim and Li teach the display apparatus according to claim 1 (see above rejection), wherein in the single frame period, a plurality of time lengths of these sub-frame periods are not entirely identical (see Li at least fig. 4B, [0040] “one frame is divided into two sub-frame time periods T1 and T2. The duration of one full frame is T, the duration of one sub-frame time period is T1=.alpha.T, and the duration of the other sub-frame time period is T2=(1-.alpha.)T, so T=T1+T2. In the example in FIG. 5, .alpha.=3/4, and thus T1=(3/4)T, and T2=(1/4)T.”; [0069] “the duration of the first sub-frame SF1 is 1/4 of the total frame time F, and the duration of the second sub-frame SF2 is the remaining 3/4 of the total frame time F.”).
As to claim 3, the combination of Kim and Li teach the display apparatus according to claim 1 (see above rejection), wherein in the single frame period, a plurality of light-emitting time ratios of these sub-frame periods are not entirely identical (see Kim at least col. 7 lines 39-50 “the emission driver 400 may generate light emission signals while shifting the light emission start signal by a horizontal period 1H”; col. 11 lines 36-62 “In the third period P3, an emission signal of a low level may be supplied to the pixel PX[i, j]”; col. 13 lines 8-36: different frame structures (first frame period vs second frame period) – note Kim teaches emission occurring in selected periods and not others, which supports different emission duty ratios across frame structures).
As to claim 4, the combination of Kim and Li teach the display apparatus according to claim 1 (see above rejection), wherein in each of these sub-frame periods of the single frame period, a plurality of light-emitting pulses of each of these emission signals have identical pulse width (see Kim at least col. 7 lines 39-50 “the emission driver 400 may generate light emission signals while shifting the light emission start signal by a horizontal period 1H, and a frequency of the emission signals may be the same as a frequency of the emission start signal.” – note row-shifted emission pulses derived from a common clock inherently have uniform pulse width within a given emission sequence).
As to claim 5, the combination of Kim and Li teach the display apparatus according to claim 4 (see above rejection), wherein in the single frame period, for each of these emission signals, a pulse width of these light-emitting pulses in a first sub-frame period among these sub-frame periods is identical to a pulse width of these light-emitting pulses in a second sub-frame period different from the first sub-frame period among these sub-frame periods (see Kim at least col. 12 line 34 – col. 13 line 36: emission frequency fixed at f1 while scan frequency varies and multiple frame periods with different repetition structures).
As to claim 6, the combination of Kim and Li teach the display apparatus according to claim 4 (see above rejection), wherein in the single frame period, for each of these emission signals, a pulse width of these light-emitting pulses in a third sub-frame period among these sub-frame periods is not identical to a pulse width of these light-emitting pulses in a fourth sub-frame period different from the third sub-frame period among these sub-frame periods (see Kim at least col. 12 line 34 – col. 13 line 36: emission frequency fixed at f1 while scan frequency varies and multiple frame periods with different repetition structures).
As to claim 7, the combination of Kim and Li teach the display apparatus according to claim 1 (see above rejection), wherein a minimum driving current for illuminating the emission element of each of these self-luminous pixel circuits is based on a characteristic curve of a forward voltage of the emission element and a current-voltage characteristic curve of a driving transistor of each of these self-luminous pixel circuits (see Kim at least col. 8 lines 48-54 “The driving transistor TD may be connected between the first power line VDDL and a third node N3 and include a gate electrode connected to a first node N1. The driving transistor TD may be turned on by a voltage applied to the first node N1 to generate a driving current and to supply the generated driving current to the emission element EL electrically connected to a fourth node N4.”; col. 10 lines 3-13 “On the other hand, when the display device DD is driven at a low frequency, the second transistor T2 and the sixth transistor T6, which are n-type transistors, may have poor leakage characteristics, so that the voltage of the gate electrode of the driving transistor TD connected to the first node N1 may fluctuate. When the voltage of the gate electrode of the driving transistor TD fluctuates, the driving current may be changed, so that the light-emitting element EL may not emit light with a desired luminance, and a flicker phenomenon may occur.”; col. 11 lines 53-62 “When the differential voltage is applied to the first node N1, the driving transistor TD may generate a driving current corresponding to the differential voltage applied to the first node N1 to transfer the driving current to the fourth transistor T4. The fourth transistor T4 may be turned on by the emission signal of the low level to transfer the driving current received from the driving transistor TD to the emission element EL, and the emission element EL may emit light with a luminance corresponding to the driving current.”).
As to claim 8, the combination of Kim and Li teach the display apparatus according to claim 1 (see above rejection), wherein each of these self-luminous pixel circuits comprises:
the emission element (see Kim at least col. 8 lines 45-47 “the pixel PX[i, j] includes .. an emission element EL”), having an anode and a cathode coupled to a system low voltage;
an emission element driving circuit, receiving a system high voltage, one of these emission signals, and a gate control voltage, and coupled to the anode of the emission element to provide the driving current to the emission element (see Kim at least col. 9 lines 5-21 “The third transistor T3 may be connected between the second node N2 and the initialization line VintL and include a gate electrode connected to the emission control line EL[i]. The third transistor T3 may be turned on by the emission signal supplied through the light emission control line El[i] to apply the initialization voltage Vint to the second node N2. The fourth transistor T4 may be connected between the third node N3 and the fourth node N4 and include a gate electrode connected to the emission control line EL[i]. The fourth transistor T4 may be turned on by the emission signal supplied through the emission control line EL[i] to electrically connect the third node N3 and the fourth node N4. That is, when the fourth transistor T4 is turned on, a driving current of the driving transistor TD may be transferred to the first electrode (or fourth node N4) of the emission element EL.”);
a data programming circuit, coupled to the gate driver to receive a first scanning signal and a second scanning signal, coupled to the emission driving circuit, and receiving one of these pixel voltages to provide the gate control voltage (see Kim at least col. 8 line 55 – col. 9 line 5 “The first transistor T1 may be connected between the data line DL[j] and a second node N2 and include a gate electrode connected to the fourth scan line SL4[i]. The first transistor T1 may be turned on by the fourth scan signal supplied through the fourth scan line SL4[i] and to supply the data signal, such as a data voltage, to the second node N2 through the data line DL[j]. The second transistor T2 may be connected between the first node N1 and the third node N3 and include a gate electrode connected to the third scan line SL3[i]. The second transistor T2 may be turned on by the third scan signal supplied through the third scan line Sl3[i] to electrically connect the first node N1 and the third node N3. That is, the second transistor T2 may allow the driving transistor TD to operate as a diode by electrically connecting the gate electrode (or first node N1) of the driving transistor TD and the second electrode (or third node N3) of the driving transistor TD.”; col. 9 lines 38-44 “The storage capacitor Cst may be connected between the second node N2 and the first node N1 to store a voltage corresponding to a data signal applied to the second node N2. For example, the storage capacitor Cst may store a difference voltage between a voltage of the data signal applied to the second node N2 and a voltage of the first node N1.”); and
a reset circuit, receiving the gate control voltage and a reset signal to reset the gate control voltage based on the reset signal (see Kim at least col. 9 lines 23-37 “The fifth transistor T5 may be connected between the initialization line VintL and the fourth node N4 and include a gate electrode connected to the first scan line SL1[i]. The fifth transistor T5 is turned on by the first scan signal supplied through the first scan line SL1[i] to apply the initialization voltage Vint to the fourth node N4. That is, when the fifth transistor T5 is turned on, the first electrode (or the fourth node N4) of the emission element EL may be initialized into the initialization voltage Vint. The sixth transistor T6 may be connected between the first node N1 and the initialization line VintL and include a gate electrode connected to the second scan line SL2[i]. The sixth transistor T6 is turned on by the second scan signal supplied through the second scan line SL2[i] to apply the initialization voltage Vint to the first node N1.”; col. 11 lines 11-15 “In the first period P1, a first scan signal of a low level may be supplied to the pixel PX[i, j] through the first scan line Sl1[i], and a second scan signal of a high level may be supplied to the pixel PX[i, j] through the second scan line SL2[i]. Accordingly, referring to FIG. 4, the fifth transistor T5 and the sixth transistor T6 may be turned on, and the first to fourth transistors T1 to T4 may be turned off. When the fifth transistor T5 is turned on, the initialization voltage Vint may be applied to the fourth node N4. Accordingly, the first electrode (or anode) of the emission element EL may be initialized with the initialization voltage Vint. When the sixth transistor T6 is turned on, the initialization voltage Vint may be applied to the first node N1. Accordingly, the gate electrode of the driving transistor TD may be initialized with the initialization voltage Vint.”).
As to claim 9, the combination of Kim and Li teach the display apparatus according to claim 8 (see above rejection), wherein the emission driving circuit comprises: a first transistor, having a first terminal receiving the system high voltage, a control terminal receiving one of these emission signals, and a second terminal; a second transistor, having a first terminal coupled to the second terminal of the first transistor, a control terminal receiving the gate control voltage, and a second terminal; and a third transistor, having a first terminal coupled to the second terminal of the second transistor, a control terminal receiving one of these emission signals, and a second terminal providing the driving current (see Kim at least col. 8 lines 48-54 “The driving transistor TD may be connected between the first power line VDDL and a third node N3 and include a gate electrode connected to a first node N1. The driving transistor TD may be turned on by a voltage applied to the first node N1 to generate a driving current and to supply the generated driving current to the emission element EL electrically connected to a fourth node N4.”; col. 9 lines 5-21 “The third transistor T3 may be connected between the second node N2 and the initialization line VintL and include a gate electrode connected to the emission control line EL[i]. The third transistor T3 may be turned on by the emission signal supplied through the light emission control line El[i] to apply the initialization voltage Vint to the second node N2. The fourth transistor T4 may be connected between the third node N3 and the fourth node N4 and include a gate electrode connected to the emission control line EL[i]. The fourth transistor T4 may be turned on by the emission signal supplied through the emission control line EL[i] to electrically connect the third node N3 and the fourth node N4. That is, when the fourth transistor T4 is turned on, a driving current of the driving transistor TD may be transferred to the first electrode (or fourth node N4) of the emission element EL.”).
As to claim 10, the combination of Kim and Li teach the display apparatus according to claim 9 (see above rejection), wherein the data programming circuit comprises: a fourth transistor, having a first terminal coupled to the control terminal of the second transistor, a control terminal receiving a scan compensation signal, and a second terminal coupled to the second terminal of the second transistor; a fifth transistor, having a first terminal receiving a reference voltage, a control terminal receiving a voltage control signal, and a second terminal coupled to the first terminal of the second transistor; a sixth transistor, having a first terminal receiving one of these pixel voltages, a control terminal receiving the first scanning signal, and a second terminal; a seventh transistor, having a first terminal receiving one of these pixel voltages, a control terminal receiving the second scanning signal, and a second terminal coupled to the second terminal of the sixth transistor; a first capacitor, coupled between the second terminal of the sixth transistor and the control terminal of the second transistor to provide the gate control voltage; a second capacitor, coupled between the second terminal of the fifth transistor and the second terminal of the sixth transistor; and an eighth transistor, having a first terminal coupled to the second terminal of the sixth transistor, a control terminal receiving the scan compensation signal, and a second terminal receiving an initial voltage (see Kim at least fig. 2: multiple scan-controlled transistors (T1–T6), capacitor Cst storing gate voltage and col. 8 line 40 – col. 9 lines 44).
As to claim 11, the combination of Kim and Li teach the display apparatus according to claim 10 (see above rejection), wherein the reset circuit comprises: a ninth transistor, having a first terminal coupled to the second terminal of the sixth transistor, a control terminal receiving the reset signal, and a second terminal receiving the initial voltage; and a tenth transistor, having a first terminal coupled to the control terminal of the second transistor, a control terminal receiving the reset signal, and a second terminal receiving the initial voltage (see Kim at least fig. 2: multiple scan-controlled transistors (T1–T6), capacitor Cst storing gate voltage, reset paths using Vint and col. 8 line 40 – col. 9 lines 44).
As to claim 16, the combination of Kim and Li teach the method of driving pixels according to claim 15 (see above rejection), wherein in the single frame period, a plurality of time lengths of the sub-frame periods are not entirely identical (see Li at least fig. 4B, [0040] “one frame is divided into two sub-frame time periods T1 and T2. The duration of one full frame is T, the duration of one sub-frame time period is T1=.alpha.T, and the duration of the other sub-frame time period is T2=(1-.alpha.)T, so T=T1+T2. In the example in FIG. 5, .alpha.=3/4, and thus T1=(3/4)T, and T2=(1/4)T.”; [0069] “the duration of the first sub-frame SF1 is 1/4 of the total frame time F, and the duration of the second sub-frame SF2 is the remaining 3/4 of the total frame time F.”).
As to claim 17, the combination of Kim and Li teach the method of driving pixels according to claim 15 (see above rejection), wherein in the single frame period, a plurality of light-emitting time ratios of the sub-frame periods are not entirely identical (see Kim at least col. 7 lines 39-50 “the emission driver 400 may generate light emission signals while shifting the light emission start signal by a horizontal period 1H”; col. 11 lines 36-62 “In the third period P3, an emission signal of a low level may be supplied to the pixel PX[i, j]”; col. 13 lines 8-36: different frame structures (first frame period vs second frame period) – note Kim teaches emission occurring in selected periods and not others, which supports different emission duty ratios across frame structures).
As to claim 18, the combination of Kim and Li teach the method of driving pixels according to claim 15 (see above rejection), wherein in each of the sub-frame periods of the single frame period, a plurality of light-emitting pulses of each of the emission signals have identical pulse width (see Kim at least col. 7 lines 39-50 “the emission driver 400 may generate light emission signals while shifting the light emission start signal by a horizontal period 1H, and a frequency of the emission signals may be the same as a frequency of the emission start signal.” – note row-shifted emission pulses derived from a common clock inherently have uniform pulse width within a given emission sequence).
As to claim 19, the combination of Kim and Li teach the method of driving pixels according to claim 18 (see above rejection), wherein in the single frame period, for each of these emission signals, a pulse width of these light-emitting pulses in a first sub-frame period among these sub-frame periods is identical to a pulse width of these light-emitting pulses in a second sub-frame period different from the first sub-frame period among these sub-frame periods (see Kim at least col. 12 line 34 – col. 13 line 36: emission frequency fixed at f1 while scan frequency varies and multiple frame periods with different repetition structures).
As to claim 20, the combination of Kim and Li teach the method of driving pixels according to claim 18 (see above rejection), wherein in the single frame period, for each of these emission signals, a pulse width of these light-emitting pulses in a third sub-frame period among these sub-frame periods is not identical to a pulse width of these light-emitting pulses in a fourth sub-frame period different from the third sub-frame period among these sub-frame periods (see Kim at least col. 12 line 34 – col. 13 line 36: emission frequency fixed at f1 while scan frequency varies and multiple frame periods with different repetition structures).
As to claim 21, the combination of Kim and Li teach the method of driving pixels according to claim 18 (see above rejection), wherein a minimum driving current for illuminating the emission element of each of these self-luminous pixel circuits is based on a characteristic curve of a forward voltage of the emission element and a current-voltage characteristic curve of a plurality of transistor of each of these self-luminous pixel circuits (see Kim at least col. 8 lines 48-54 “The driving transistor TD may be connected between the first power line VDDL and a third node N3 and include a gate electrode connected to a first node N1. The driving transistor TD may be turned on by a voltage applied to the first node N1 to generate a driving current and to supply the generated driving current to the emission element EL electrically connected to a fourth node N4.”; col. 10 lines 3-13 “On the other hand, when the display device DD is driven at a low frequency, the second transistor T2 and the sixth transistor T6, which are n-type transistors, may have poor leakage characteristics, so that the voltage of the gate electrode of the driving transistor TD connected to the first node N1 may fluctuate. When the voltage of the gate electrode of the driving transistor TD fluctuates, the driving current may be changed, so that the light-emitting element EL may not emit light with a desired luminance, and a flicker phenomenon may occur.”; col. 11 lines 53-62 “When the differential voltage is applied to the first node N1, the driving transistor TD may generate a driving current corresponding to the differential voltage applied to the first node N1 to transfer the driving current to the fourth transistor T4. The fourth transistor T4 may be turned on by the emission signal of the low level to transfer the driving current received from the driving transistor TD to the emission element EL, and the emission element EL may emit light with a luminance corresponding to the driving current.”).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 11,176,874 B2) in view of Li et al. (US 2015/0077446 A1), further in view of Chaji (USPN 11,074,863 B2).
As to claim 12, the combination of Kim and Li teach the display apparatus according to claim 8 (see above rejection).
Kim and Li do not directly teach wherein each of the self-luminous pixel circuits further comprises a test circuit coupled to the anode of the emission element and receiving a test signal to provide a test output voltage based on the test signal.
Chaji teaches wherein each of the self-luminous pixel circuits further comprises a test circuit coupled to the anode of the emission element and receiving a test signal to provide a test output voltage based on the test signal (see at least col. 9 line 51 – col. 10 line 3 “The source terminal of the drive transistor 112 is electrically coupled to an anode terminal of the OLED 114.”; col. 14 lines 8-19 “This circuit includes a monitor line 28j coupled to the node 430 by a read transistor 422 controlled by a RD line 420”; col. 15 lines 52-60 “The monitor line 28j is connected to the source of the drive transistor 712 during the interval when the RD line is low to turn on the read transistor 726, so that a reading of the voltage on the anode of the OLED 714 can be taken via the monitor line 28j.”).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to incorporate Chaji’s monitor/read test path into the display apparatus of Kim as modified by Li in order to measure pixel operating parameters (e.g., OLED/anode voltage and/or drive current) for testing, calibration, and compensation, which is a known design objective in active-matrix self-luminous displays, yielding predictable results (i.e., providing a readable test output on a monitor line when a read/test signal is asserted). Chaji itself explains the purpose of the monitor line: see col. 8 line 33 – col. 9 line 8 “The monitor line allows the monitoring system 12 to measure a current or voltage associated with the pixel 10 … The monitoring system 12 can also extract an operating voltage of the light emitting device”).
As to claim 13, the combination of Kim, Li and Chaji teach the display apparatus according to claim 12 (see above rejection), wherein the test circuit comprises: an eleventh transistor, having a first terminal coupled to the anode of the emission element, a control terminal receiving the test signal, and a second terminal providing the test output voltage (see Chaji at least col. 9 line 51 – col. 10 line 3 “The source terminal of the drive transistor 112 is electrically coupled to an anode terminal of the OLED 114.”; col. 14 lines 8-19 “This circuit includes a monitor line 28j coupled to the node 430 by a read transistor 422 controlled by a RD line 420”; col. 15 lines 52-60 “The monitor line 28j is connected to the source of the drive transistor 712 during the interval when the RD line is low to turn on the read transistor 726, so that a reading of the voltage on the anode of the OLED 714 can be taken via the monitor line 28j.” – note Chaji’s read transistor (e.g., 422/726) maps to the claimed “eleventh transistor,” and the monitor line voltage maps to the claimed “test output voltage.”).
Claims 14 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 11,176,874 B2) in view of Li et al. (US 2015/0077446 A1), further in view of Shin et al. (USPN 10,847,572 B2).
As to claim 14, the combination of Kim and Li teach the display apparatus according to claim 1 (see above rejection).
Kim and Li do not directly teach wherein the emission element comprises a micro light-emitting diode.
Shin teaches wherein the emission element comprises a micro light-emitting diode (see at least col. 4 lines 31-41 “The present invention provides a micro light emitting diode (LED) display device .. . a micro LED display device may be formed by flip-chip bonding a micro LED panel including a plurality of micro LED pixels”; col. 4 lines 50-58 “the micro LED panel (or the micro LED array) 100 according to the present invention is an LED panel including an array structure in which a plurality of LEDs (that is, a plurality of micro LED pixels) … , the plurality of micro LED pixels is arranged on the wafer in rows and columns”).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to implement the self-luminous display apparatus of Kim (as modified by Li) using micro LED emission elements as taught by Shin, because micro LEDs were a known alternative class of self-luminous emitters to OLEDs, offering predictable benefits such as higher luminance, longer lifetime, and improved efficiency. Substituting one known self-luminous emission element (OLED) with another known self-luminous emission element (micro LED) constitutes a simple substitution of one known equivalent for another yielding predictable results.
As to claim 22, the combination of Kim and Li teach the method of driving pixels according to claim 15 (see above rejection).
Kim and Li do not directly teach wherein the emission element comprises a micro light-emitting diode.
Shin teaches wherein the emission element comprises a micro light-emitting diode (see at least col. 4 lines 31-41 “The present invention provides a micro light emitting diode (LED) display device .. . a micro LED display device may be formed by flip-chip bonding a micro LED panel including a plurality of micro LED pixels”; col. 4 lines 50-58 “the micro LED panel (or the micro LED array) 100 according to the present invention is an LED panel including an array structure in which a plurality of LEDs (that is, a plurality of micro LED pixels) … , the plurality of micro LED pixels is arranged on the wafer in rows and columns”).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to implement the self-luminous display apparatus and method of driving pixels of Kim (as modified by Li) using micro LED emission elements as taught by Shin, because micro LEDs were a known alternative class of self-luminous emitters to OLEDs, offering predictable benefits such as higher luminance, longer lifetime, and improved efficiency. Substituting one known self-luminous emission element (OLED) with another known self-luminous emission element (micro LED) constitutes a simple substitution of one known equivalent for another yielding predictable results.
Response to Arguments
Applicant’s arguments filed 4/24/2026 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JENNIFER L ZUBAJLO/Examiner, Art Unit 2627 6/10/2026
/KE XIAO/Supervisory Patent Examiner, Art Unit 2627
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