Prosecution Insights
Last updated: October 02, 2026
Application No. 18/976,352

PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE DEVICE AND SYSTEM INCLUDING THE SAME

Final Rejection §103
Filed
Dec 11, 2024
Priority
Feb 18, 2021 — RE 10-2021-0022109 +2 more
Examiner
ABRAHAM, ESAW T
Art Unit
2112
Tech Center
2100 — Computer Architecture & Software
Assignee
SK hynix Inc.
OA Round
2 (Final)
94%
Grant Probability
Favorable
3-4
OA Rounds
3m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
1029 granted / 1092 resolved
+39.2% vs TC avg
Minimal +3% lift
Without
With
+3.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
20 currently pending
Career history
1115
Total Applications
across all art units

Statute-Specific Performance

§101
20.0%
-20.0% vs TC avg
§103
13.2%
-26.8% vs TC avg
§102
17.9%
-22.1% vs TC avg
§112
31.4%
-8.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1092 resolved cases

Office Action

§103
DETAILED ACTION Response to Arguments Applicants’ arguments filed 07/16/2026 have been fully considered but they are not persuasive. Applicant's arguments are summarized below: Applicants’ Argument: Sharma at Paragraphs [0080] and [0126], Sharma merely discloses a feature that NOP packets may not contain TLP (Transaction Layer Packet) or DLLP (Data Link Layer Packet) and a feature that the receiver uses a transmitted NOP packet to check errors. Checking errors here means transmitting NOP packet with only "0 bit" in TLP, not transmitting NOP packet including "information" such as a trigger point of a dump operation and an occurrence time of the event. Examiner's Response: Sharma in FIG. 5A clearly illustrates a logic circuitry of a protocol stack 500 of a transmitter side of the microarchitecture. The protocol stack 500 can include transaction layer (TL) queues 508a, a No Operation transaction layer packet (NOP TLP) generator 510, and a TX retry buffer 516. The TL queues 508a can include logic to store or buffer outbound transaction layer information, payload data, control data, etc. for an outbound packet. The NOP TLP generator 510 can generate NOP TLPs that can be included in a NOP flit that is transmitted by the transmitter across the link (see paragraph [0080]). Applicants’ Argument: Examiner has acknowledged that Sharma does not teach a NOP packet which includes a trigger point of a dump operation and an occurrence time of the event and Reeves teaches a trigger point of a dump operation and an occurrence of the event. However, Reeves remains silent regarding the feature of transmitting the NOP packet which includes a trigger point of a dump operation and an occurrence time of the event. Examiner's Response: Reeves discloses packet boundary track unit 450 ensures that the injected packets do not collide with the forwarded packets by providing control signals to multiplexer 430 at the correct time; thereby allowing the waiting packet to be injected to be scrambled and transmitted by transmit unit 435. Assuming that there are packets to be injected stored within injection FIFO 425 and packets to be forwarded stored within holding FIFO 420, packet boundary track unit 450 may selectively control multiplexer 430 to pass either type of packet to transmit unit 435 depending upon a fairness algorithm. The fairness algorithm may be any algorithm configured to prevent starvation of either the injected packets or the forwarded packets for any given memory module. It is noted that NOP packets received on uplink 411B may be discarded instead of being stored within holding FIFO 420 or being forwarded (see col. 5, lines 5-22). Further, Reeves teaches that busy pulse injection unit 355 is configured to provide an indication corresponding to the number of busy pulses received from upstream to uplink control unit 241 of FIG. 2. In one embodiment, if a memory module is the last module in the serially connected chain, uplink control unit 241 may cause one or more NOP packets to be injected into the upstream transaction sequence dependent upon the number of busy pulses received on busy signal 371. For example, in one implementation, for every two busy pulses received, uplink control unit 241 may cause one NOP packet to be injected into the upstream transaction sequence. Furthermore, the references are not required to teach the exact claim language (i.e., trigger point of a dump operation and an occurrence time of the event) to that of the present invention and the concepts are taught in both references to the extent required by the actual claim language. Furthermore, the interpretation of the claim language must be as broad as possible for the given art. If the Applicant needs a specific interpretation of the claim language, these details must be imported into the claims. These details cannot be read into the claim language when the claim language is so broad as to encompass other valid interpretations. Applicants are advised to review references in their entirety for a complete and better understanding of the prior art applied. This may enhance the Applicants ability to formulate claim language that includes novelty of the application. It is the Examiner's conclusion that the claims of the present application, as presented, are not patentably distinct or novel over the prior arts of record. Applicants are encouraged to formulate claim language that clearly differentiates the claims from the prior art of record. Therefore, the applicants’ argument, although acknowledged, has not been found to be convincing. Double Patenting The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 1-10 are rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claim 1-14 of U.S. Patent No. 11,726,870. Claim 1 of the present application teaches "A method of operating a PCle (Peripheral Component Interconnect Express) device, the method comprising: generating a NOP packet including event information, in response to occurrence of an event; and transmitting the NOP packet to an external device through a link including a plurality of lanes, wherein the event information includes a trigger point of a dump operation and an occurrence time of the event". Whereas claim 1 of U.S. PN:11,726,870 teaches "A peripheral component interconnect express (PCle) interface device, comprising: a No Operation (NOP) data link layer packet (DLLP) generator configured to generate a NOP DLLP including event information representing a trigger point of a dump operation, event in response to occurrence of an event; and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes, wherein the event information is used to specify an occurrence time of the event". RATIONALS: Claims 1 of the instant application and claim 1 of U.S. Patent No. 11,726,870 are generally directed to different statutory embodiments of the same invention. That is, claim 1 of the instant application is directed to a method, while claim 1 of U.S. Patent No. 11,726,870. is directed to a machine. Although the conflicting claims are not identical, they are not patentably distinct from each other because claim 1 of the instant application is the method version of the machine limitations cited in claim 1 of U.S. patent no. 11,726,870. Therefore, the claims are obvious variations of each other and not patentably distinct. Claim 7 of the present application teaches "A method of operating a PCle (Peripheral Component Interconnect Express) system, the method comprising: generating, by a first PCle device, a NOP packet including event information, in response to occurrence of an event; transmitting, by the first PCle device, the NOP packet to a second PCle device through a link including a plurality of lanes; and performing, by the second PCle device, a dump operation storing information about data and packets transmitted and received during a set time period including a time at which the second PCle device receives the NOP packet from the first PCle device, and wherein the event information includes a trigger point of the dump operation and an occurrence time of the event". Whereas claim 8 of U.S. PN: 11,726,870 teaches "a peripheral component interconnect express (PCle) system, comprising: a first PCle device configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing a trigger point of a dump operation, in response to occurrence of an event, and to transmit the NOP DLLP through a link including a plurality of lanes; and a second PCle device configured to, when the NOP DLLP is received from the first PCle device, perform the dump operation for storing information about data and packets transmitted and received during a set time period including a time at which the NOP DLLP is received, wherein the event information is used to specify an occurrence time of the event". Dependent claims 2-6 and 8-10 of the instant application have corresponding issues with the dependent claims 1-7 and 9-14 of U.S. patent no. U.S. PN: 11,726,870 are also rejected under non-statutory obviousness-type double patenting. RATIONALS: Claims 7 of the instant application and claim 8 of U.S. Patent No. 11,726,870. is generally directed to different statutory embodiments of the same invention. That is, claim 1 of the instant application is directed to a method, while claim 8 of U.S. Patent No. 11,726,870. is directed to a machine. Although the conflicting claims are not identical, they are not patentably distinct from each other because claim 7 of the instant application is the method version of the machine limitations cited in claim 8 of U.S. patent no. 11,726,870. Therefore, the claims are obvious variations of each other and not patentably distinct. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or non-obviousness. Claims 1-10 are rejected under 35 U.S.C. 103(a) as being unpatentable over Sharma US PUB No. 2020/0364129 (Hereinafter Sharma) in view of Reeves et al. "herein Reeves" (U.S. PN: 7,016,213). Regarding claim 1, Sharma substantially teaches a method of operating a PCle (Peripheral Component Interconnect Express) device (see Figure 5A/B, par. [0045], [0145]), the method comprising: generating a NOP packet including event information in response to occurrence of an event (see par. [0148]; and transmitting the NOP packet to an external device through a link including a plurality of lanes (see Figure 5A/B, ref. (510) & (520) and par. [0079] - [0081 and par. [0145] - [0148]), wherein the event information includes a trigger point of a dump operation and an occurrence time of the event Sharma substantially teaches the claimed invention described in claim 1 (as indicated above). However, Sharma does not explicitly teach a trigger point of a dump operation and an occurrence time of the event Reeves, in an analogous art, teaches a trigger point of a dump operation and an occurrence time of the event "Assuming that there are packets to be injected stored within injection FIFO 425 and packets to be forwarded stored within holding FIFO 420, packet boundary track unit 450 may selectively control multiplexer 430 to pass either type of packet to transmit unit 435 depending upon a fairness algorithm. The fairness algorithm may be any algorithm configured to prevent starvation of either the injected packets or the forwarded packets for any given memory module. It is noted that NOP packets received on uplink 411B may be discarded instead of being stored within holding FIFO 420 or being forwarded" (see col. 9, lines 2-22). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Sharma with the teachings of Reeves by including dump operation and an occurrence time of the event. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention because one of ordinary skill in the art would have recognized that a trigger point of a dump operation and an occurrence time of the even would have provided reliable reception of transmitted data. Regarding claim 2, Sharma teaches: the generating the NOP packet sets at least one bit of a plurality of bits in a support field of the NOP packet (see Figure 5A/B, ref. (510) & (520) and par. [0079] - [0081 and par. [0145] - [0148] in Sharma). Regarding claim 3, Reeves teaches: discarding the NOP packet in response to a data integrity check (see col. 9, lines 2-22 in Reeves). Regarding claim 4, Sharma teaches: wherein the transmitting the NOP packet repeatedly transmits the NOP packet during a preset time period (Figure 7, steps (714) & (716) and sections [0130] - [0132] in Sharma). Regarding claim 5, Sharma teaches: storing data, transmitted and received during a preset time period including the occurrence time of the event, and information about a communication environment in response to the occurrence of the event (Figure 7, steps (714) & (716) and sections [0130] - [0132] in Sharma). In regard to claim 6, Sharma teaches: wherein the event includes information on at least one of a timeout of a link training and status state machine (LTSSM), occurrence of link-down due to the timeout of the LTSSM, occurrence of a parity error, a temperature rise prevention operation (Figures 5A/B and sections [0060] and [0199] in Sharma). In regard to claim 7, Sharma substantially teaches a method of operating a PCle (Peripheral Component Interconnect Express) system, the method comprising: generating, by a first PCle device, a NOP packet including event information, in response to occurrence of an event; transmitting, by the first PCle device, the NOP packet to a second PCle device through a link including a plurality of lanes; (Figure 2A, ref. (202) & (204) and sections [0045] - -[0046] in Sharma) and performing, by the second PCle device, a dump operation storing information about data and packets transmitted and received during a set time period including a time at which the second PCle device receives the NOP packet from the first PCle device (Figure 2A, ref. (208) & (206) and sections [0045] - [0047] in Sharma). Sharma substantially teaches the claimed invention described in claim 7 (as indicated above). However, Sharma does not explicitly teach a trigger point of a dump operation and an occurrence time of the event Reeves, in an analogous art, teaches a trigger point of a dump operation and an occurrence time of the event "Assuming that there are packets to be injected stored within injection FIFO 425 and packets to be forwarded stored within holding FIFO 420, packet boundary track unit 450 may selectively control multiplexer 430 to pass either type of packet to transmit unit 435 depending upon a fairness algorithm. The fairness algorithm may be any algorithm configured to prevent starvation of either the injected packets or the forwarded packets for any given memory module. It is noted that NOP packets received on uplink 411B may be discarded instead of being stored within holding FIFO 420 or being forwarded" (see col. 9, lines 2-22). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Sharma with the teachings of Reeves by including dump operation and an occurrence time of the event. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention because one of ordinary skill in the art would have recognized that a trigger point of a dump operation and an occurrence time of the even would have provided reliable reception of transmitted data. In regard to claim 8, Sharma teaches: storing, by the first PCle device, data, transmitted and received during a preset time period including the occurrence time of the event, and information about a communication environment in response to the occurrence of the event (Figure 7, steps (714) & (716) and sections [0130]-[0132] in Sharma). Regarding claim 9, Sharma teaches: wherein the transmitting the NOP packet repeatedly transmits the NOP packet during a preset time period by the first PCle device (Figure 7, steps (714) & (716) in Sharma). In regard to claim 10, Sharma teaches: wherein the event includes information on at least one of a timeout, the timeout of a link training and status state machine (LTSSM), a link-down, occurrence of the link-down due to the timeout of the LTSSM, occurrence of a parity error, a temperature rise prevention operation (see Figures 5A/5B and sections [0060] and [0199] in Sharma). Conclusion THIS ACTION IS MADE FINAL. Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for replying to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ESAW T ABRAHAM whose telephone number is (571)272-3812. The examiner can normally be reached on 8AM-4:30PM EST M-F. If attempts to reach the examiner by telephone are unsuccessful, the examiner'ssupervisor, Albert DeCady can be reached on (571) 272-3819. The fax phonenumber for the organization where this application or proceeding is assigned is(703) 872-9306. of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ESAW T ABRAHAM/Primary Examiner, Art Unit 2112
Read full office action

Prosecution Timeline

Dec 11, 2024
Application Filed
Apr 27, 2026
Non-Final Rejection mailed — §103
Jul 16, 2026
Response Filed
Sep 15, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12750068
APPARATUS AND METHOD FOR POWER REDUCTION IN A BIT FLIPPING DECODER
2y 6m to grant Granted Sep 29, 2026
Patent 12739056
METHOD AND TRANSMITTER FOR TRANSMITTING DATA USING CONSTELLATION
2y 0m to grant Granted Sep 15, 2026
Patent 12726217
METHOD AND APPARATUS FOR LOW DENSITY PARITY CHECK CHANNEL CODING IN WIRELESS COMMUNICATION SYSTEM
2y 1m to grant Granted Sep 01, 2026
Patent 12718134
GENERATING OPTIMAL SAMPLES IN QUANTUM OPTIMIZATION ALGORITHMS
3y 1m to grant Granted Aug 25, 2026
Patent 12705132
NON-VOLATILE MEMORY METADATA PROTECTION
2y 2m to grant Granted Aug 11, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
94%
Grant Probability
97%
With Interview (+3.2%)
2y 1m (~3m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1092 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month