DETAILED ACTION
Claims 1, 3-21 are pending. Claim 2 is cancelled.
Priority: 12/11/2024
Assignee: Mellanox
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 18-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 is rejected under 35 U.S.C. § 112(b) as being indefinite because the claim recites “receiving, by a selector memory, the plurality of memory responses from a memory input/output interface,” but subsequently recites receiving the responses “from the selector.” It is unclear whether “selector memory” is intended to identify the claimed selector, a memory functioning as a selector, or a separate component. The specification identifies selectors 16 and 22 but does not identify a “selector memory.” Accordingly, the metes and bounds of the claimed selector limitation are not reasonably clear. Claims 19–21 depend from claim 18 and incorporate the same indefinite limitation.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 19 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 19 is rejected under 35 U.S.C. § 112(d) because it depends from claim 18 but does not appear to specify a further limitation of the subject matter claimed. Claim 18 already requires determining whether to send a given memory response directly to a respective processor or to the shared reorder buffer, and claim 19 repeats substantially the same determining step.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4, 7, 16, 17, 18, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai(20210294765), and further in view of Kwon et al.(20120159037).
As per claim 1, Lai discloses:
A system for handling out-of-order memory responses of a plurality of memory responses to memory requests in a multi-processor environment(Lai, [0019 -- As shown in FIG. 2, the system 100 may comprise a slave device 140 and one or more master devices such as N master devices 120_1, . . . and 120_N, where N is a positive integer. The slave device 140 may comprise an atomizer 141, an RRB 142 and a memory device 143, where the atomizer 10, the RRB 20 and the memory device 30 shown in FIG. 1 may be examples of the atomizer 141, the RRB 142 and the memory device 143, respectively.]), the system comprising:
a plurality of processors(Lai, [0019 -- the system 100 may comprise a slave device 140 and one or more master devices such as N master devices 120_1, . . . and 120_N, where N is a positive integer]);
a shared reorder buffer coupled to the plurality of processors(Lai, [0019 -- The slave device 140 may comprise an atomizer 141, an RRB 142 and a memory device 143, where the atomizer 10, the RRB 20 and the memory device 30 shown in FIG. 1 may be examples of the atomizer 141, the RRB 142 and the memory device 143, respectively. In this embodiment, the memory device 143 may be configured to store data, and the one or more master devices such as the master devices 120_1, . . . and 120_N may be coupled to the slave device 140 through a transmission interface]);
and each routing logic unit is configured to determine whether to send a given memory response directly to the respective processor or to the shared reorder buffer(Lai, [0030 -- In Step 316, the memory device 143 may determine whether a transaction ID corresponding to this data is unique according to an LSB of a response ID. If the determination is “Yes”, e.g. the response ID is {Tag_ID[k:1], 1′b1} as shown in FIG. 5, the flow enters Step 322; if the determination is “No”, e.g. the response ID is {cmd_index, 1′b0} as shown in FIG. 4, the flow enters Step 318.]);
and a plurality of transaction identification (ID) assignment logic units, each associated with a respective processor of the plurality of processors(Lai, [0017 -- Under a condition where the memory device 30 performs access control with a fixed burst length (e.g. by receiving commands with the fixed burst length), the atomizer 10 reads a command with a transaction identifier (ID) (e.g. a tag ID)], [0019 -- For example, the master device 120_1 may utilize a master core circuit therein to send a transaction ID (e.g. a tag ID) Master_Tag_ID(0), and utilize a core wrapper therein to add an attribute Is_unique_ID(0) of the transaction ID Master_Tag_ID(0) by an extension field, where the master interface 162_1 may further add an attribute Master_ID(0) of the transaction ID Master_Tag_ID(0) by an extension field]), wherein:
each transaction ID assignment logic unit is to assign transaction IDs to the memory requests issued by the respective processor(Lai, [0019 -- For example, the master device 120_1 may utilize a master core circuit therein to send a transaction ID (e.g. a tag ID) Master_Tag_ID(0), and utilize a core wrapper therein to add an attribute Is_unique_ID(0) of the transaction ID Master_Tag_ID(0) by an extension field, where the master interface 162_1 may further add an attribute Master_ID(0) of the transaction ID Master_Tag_ID(0) by an extension field]);
and the shared reorder buffer is to store and reorder ones of the plurality of memory responses stored in the shared reorder buffer based on the assigned transaction IDs(Lai, [0021 -- For example, when the attribute Is_unique_ID(n) indicates that the transaction ID Master_Tag_ID(n) is not unique in the system 100 (e.g. Is_unique_ID(n) is “0”), the RRB 142 may receive data corresponding to the transaction ID Master_Tag_ID(n) from the memory device 143, to allow this data to be sent from the slave device 140 to the master device 120_n in the in-order manner (e.g. sent in the predetermined order).], [0050 -- Thus, when the slave device 149 receives multiple read commands from different master devices, corresponding response data can be re-ordered to achieve the optimal performance.]).
Lai does not explicitly disclose the following, however Kwon discloses:
a selector configured to receive the plurality of memory responses from a memory input/output interface(Kwon, [0049 -- Each of the master IPs 600, 601, and 602, the on-chip network 500, the MIDs 100 and 101, and each of the slave IPs 700 and 701 are connected with one another via a bus including a plurality of channels], [0068 -- The R channel block 310 is used to transmit read data to the crossbar switch 400 and includes a fourth selector], [0080 -- read data includes ID information RID corresponding to the ARID of the master IP 600 that has originally output the read memory request and is thus transmitted to the SI 200 connected to the master IP 600 by the selector 311]);
a plurality of routing logic units, each routing logic unit corresponding to a respective one of the plurality of processors(Kwon, [0080 -- The slave IP 700 reads data from a memory device in response to the read memory request received through the AR channel AR(1)-700 and transmits the read data to an R channel R(1)-700 of the R channel block 310 of the MI 300. The read data includes ID information RID corresponding to the ARID of the master IP 600 that has originally output the read memory request and is thus transmitted to the SI 200 connected to the master IP 600 by the selector]),;
wherein each routing logic unit is configured to receive respective ones of the plurality of memory responses from the selector(Kwon, [0068 -- The R channel block 310 is used to transmit read data to the crossbar switch 400 and includes a fourth selector 311, which receives the data read from the slave IP 700 or 701 in response to the request and transmits the read data to the R channel block 210 of the SI 200 with reference to an ID padding RID in the read data], [0080 -- The read data is transmitted to the R channel block 210 of the SI 200 through the R channel of the crossbar switch 400 and then input to the reorder buffer 211.]);
It would have been obvious to apply the shared-reorder-buffer and bypass response-control technique of Lai to the master-corresponding response paths of Kwon because Kwon teaches routing and reordering returned responses for the corresponding masters to preserve required ordering while preventing deadlock and maximizing memory parallelism(Kwon, 0042).
As per claim 3, the system of claim 1 is incorporated, in addition, Lai discloses:
wherein each routing logic unit is to send the given memory response directly to the respective processor if the given memory response corresponds to an earliest-assigned transaction ID memory response not yet been received by the respective processor(Lai, [0033 -- In Step 322, the slave device 140 may bypass the RRB 142, and remove the extension bits from the transaction ID.], [0034 -- In Step 324, the slave device 140 may send the response data to a master device (e.g. the master device 120_n).]).
As per claim 4, the system of claim 3 is incorporated, in addition, Lai discloses:
wherein each routing logic unit is to send the given memory response to the shared reorder buffer if the memory response does not correspond to the earliest-assigned transaction ID memory response not yet been received by the respective processor(Lai, [0031 -- In Step 318, the slave device 140 may store the response data into the storage region 142B within the RRB 142 with an RRB write index {cmd_index, W_pointer} (which may correspond to an index RRB_index of the storage region 142B)]).
As per claim 7, the system of claim 1 is incorporated, in addition, Lai discloses:
the selector is to route the memory responses stored in the shared reorder buffer to appropriate ones of the processors based on initiator IDs included in the memory responses(Lai, [0032 -- In Step 320, the slave device 140 may output valid data and the transaction ID Tag_ID from a top entry of the RRB 142 (e.g. the storage region 142A and/or 142B) through a selecting circuit 240 (labeled “MUX” for brevity) within the transaction ID mapping and RRB controller], [0034 -- In Step 324, the slave device 140 may send the response data to a master device (e.g. the master device 120_n).]).
As per claim 16, the system of claim 1 is incorporated, in addition, Lai discloses:
wherein the shared reorder buffer is to maintain separate per processor ordering for the ones of the plurality of memory responses(Lai, [0049 -- In Step 410, the slave device 140 may allocate the one or more entries of the RRB 142 and perform grouping according to the attribute Master_ID(n) (e.g. mapping the attribute Master_ID(n) to a group ID Group_ID through a mapping circuit 260 within the transaction ID mapping and RRB controller 200, as shown in FIG. 8]).
As per claim 17, the system of claim 16 is incorporated, in addition, Lai discloses:
wherein the shared reorder buffer does not enforce ordering between the ones of the plurality of memory responses associated with different processors(Lai, [0050 -- As mentioned above, as the RRB 142 may be grouped into multiple groups respectively corresponding to the master devices 120_1, . . . and 120_N, data response operations of transaction IDs from different master devices may be performed independently.]).
As per claim 18, Lai discloses:
A method for handling out of order memory responses of a plurality of memory responses to memory requests in a multi processor environment(Lai, [0019 -- As shown in FIG. 2, the system 100 may comprise a slave device 140 and one or more master devices such as N master devices 120_1, . . . and 120_N, where N is a positive integer. The slave device 140 may comprise an atomizer 141, an RRB 142 and a memory device 143, where the atomizer 10, the RRB 20 and the memory device 30 shown in FIG. 1 may be examples of the atomizer 141, the RRB 142 and the memory device 143, respectively.]), the method comprising:
determining, by each routing logic unit, whether to send a given memory response directly to a respective processor of a plurality of processors or to a shared reorder buffer(Lai, [0030 -- In Step 316, the memory device 143 may determine whether a transaction ID corresponding to this data is unique according to an LSB of a response ID. If the determination is “Yes”, e.g. the response ID is {Tag_ID[k:1], 1′b1} as shown in FIG. 5, the flow enters Step 322; if the determination is “No”, e.g. the response ID is {cmd_index, 1′b0} as shown in FIG. 4, the flow enters Step 318.]);
assigning transaction IDs to the memory requests issued by the plurality of processors(Lai, [0019 -- For example, the master device 120_1 may utilize a master core circuit therein to send a transaction ID (e.g. a tag ID) Master_Tag_ID(0), and utilize a core wrapper therein to add an attribute Is_unique_ID(0) of the transaction ID Master_Tag_ID(0) by an extension field, where the master interface 162_1 may further add an attribute Master_ID(0) of the transaction ID Master_Tag_ID(0) by an extension field]);
and storing and reordering ones of the plurality of memory responses stored in the shared reorder buffer based on the assigned transaction IDs in the shared reorder buffer shared for use by the plurality of processors(Lai, [0021 -- For example, when the attribute Is_unique_ID(n) indicates that the transaction ID Master_Tag_ID(n) is not unique in the system 100 (e.g. Is_unique_ID(n) is “0”), the RRB 142 may receive data corresponding to the transaction ID Master_Tag_ID(n) from the memory device 143, to allow this data to be sent from the slave device 140 to the master device 120_n in the in-order manner (e.g. sent in the predetermined order).], [0050 -- Thus, when the slave device 149 receives multiple read commands from different master devices, corresponding response data can be re-ordered to achieve the optimal performance.]).
Lai does not explicitly disclose the following, however Kwon discloses:
receiving, by a selector memory, the plurality of memory responses from a memory input/output interface(Kwon, [0049 -- Each of the master IPs 600, 601, and 602, the on-chip network 500, the MIDs 100 and 101, and each of the slave IPs 700 and 701 are connected with one another via a bus including a plurality of channels], [0068 -- The R channel block 310 is used to transmit read data to the crossbar switch 400 and includes a fourth selector], [0080 -- read data includes ID information RID corresponding to the ARID of the master IP 600 that has originally output the read memory request and is thus transmitted to the SI 200 connected to the master IP 600 by the selector 311]);
receiving, by each routing logic unit of a plurality of routing logic units, respective ones of the plurality of memory responses from the selector(Kwon, [0068 -- The R channel block 310 is used to transmit read data to the crossbar switch 400 and includes a fourth selector 311, which receives the data read from the slave IP 700 or 701 in response to the request and transmits the read data to the R channel block 210 of the SI 200 with reference to an ID padding RID in the read data], [0080 -- The read data is transmitted to the R channel block 210 of the SI 200 through the R channel of the crossbar switch 400 and then input to the reorder buffer 211.]);
It would have been obvious to apply the shared-reorder-buffer and bypass response-control technique of Lai to the master-corresponding response paths of Kwon because Kwon teaches routing and reordering returned responses for the corresponding masters to preserve required ordering while preventing deadlock and maximizing memory parallelism(Kwon, 0042).
As per claim 19, the rejection of claim 18 is incorporated, in addition, Lai discloses:
determining whether to send a given memory response directly to a respective one of the plurality of processors or to the shared reorder buffer(Lai, [0030 -- In Step 316, the memory device 143 may determine whether a transaction ID corresponding to this data is unique according to an LSB of a response ID. If the determination is “Yes”, e.g. the response ID is {Tag_ID[k:1], 1′b1} as shown in FIG. 5, the flow enters Step 322; if the determination is “No”, e.g. the response ID is {cmd_index, 1′b0} as shown in FIG. 4, the flow enters Step 318.]).
Claim(s) 20 are directed to method steps that are implemented by the system/apparatus claim 7.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai(2021/0294765), in view of Kwon et al.(20120159037), and further in view of Dugan et al.(2024/0069795).
As per claim 5, the system of claim 1 is incorporated, in addition Lai, Kwon does not explicitly disclose the following, however, Dugan discloses:
wherein the shared reorder buffer includes flip flops to allow simultaneous comparisons between transaction IDs of the memory responses stored in the shared reorder buffer and earliest-assigned transaction IDs per clock cycle(Dugan, [0065 -- It is to be understood that requests sent on different channels of the multiple channel interface may be reordered substantially in parallel. That is, multiple instances of reordering system 600 may be used to reorder each response of the multiple requests received in parallel. In the example of FIG. 6, four instances of reordering system 600 may be used to reorder responses in parallel.]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Dugan into the system of Lai, Kwon for the benefit of maintaining memory coherency between the CPU memory space and memory on attached devices or accelerators, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost(Dugan, 0036).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai(2021/0294765), in view of Kwon et al.(20120159037), and further in view of Shaikli(2003/0214949).
As per claim 6, the system of claim 1 is incorporated, in addition, Lai, Kwon does not explicitly disclose the following, however Shaikli discloses:
wherein the shared reorder buffer includes static random access memory (SRAM) to reduce area requirements(Shaikli, [0051 -- In one embodiment, the reordering system may be implemented in a single integrated circuit (IC chip), where tables and/or memory that are used to reorder the packets are implemented in an off-chip memory (SDRAM or SRAM)]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Shaikli into the system of Lai, Kwon for the benefit of maintaining transmission efficiency as the data packets are output in selected order. Delayed data packets at destination processor is not excessively delayed or blocked by providing a dequeue logic(Shaikli, 0007).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai(2021/0294765), in view of Kwon et al.(20120159037), and further in view of Richards et al.(2014/0269760).
As per claim 8, the system of claim 1 is incorporated, in addition, Lai, Kwon does not explicitly disclose the following, however Richards discloses:
wherein each transaction ID assignment logic unit is to maintain a First In First Out (FIFO) buffer of assigned transaction IDs(Richards, [0027 -- Each picker sets a bit for each output port that it reserves in each arbitration packet (two in the example of FIG. 4). As each request is placed in a packet, the particulars of that request are transferred to the FIFO being filled for the output queue involved in that request. ]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Richards into the system of Lai, Kwon for the benefit of according to the placement of the requests in the arbitration packet, the arbitration packet is masked with a bit mask to identify any unfilled output terminals with minimal complexity(Richards, 0036).
As per claim 9, the system of claim 8 is incorporated, in addition, Lai, Kwon does not explicitly disclose the following, however Richards discloses:
wherein the shared reorder buffer is configured to receive an earliest-assigned transaction ID from the FIFO buffer of each of the transaction ID assignment logic units(Richards, [0041 -- For example, considering Bank 0, the entry from arbitration packet 83 was placed at T3, but the entry from arbitration packet 84, which is behind arbitration packet 83 was placed at T2. Thus, in one approach, a per output port reordering can be performed (212 in FIG. 8).]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Richards into the system of Lai, Kwon for the benefit of according to the placement of the requests in the arbitration packet, the arbitration packet is masked with a bit mask to identify any unfilled output terminals with minimal complexity(Richards, 0036).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai(2021/0294765), in view of Kwon et al.(20120159037), in view of Richards et al.(2014/0269760), and further in view of Tune et al.(2019/0266010).
As per claim 10, the system of claim 9 is incorporated, in addition, in addition, Lai, Kwon in view of Richards does not explicitly disclose the following, however Tune discloses:
wherein the shared reorder buffer is configured to send a signal to one of the transaction ID assignment logic units when a transaction ID of a given memory response received by the shared reorder buffer has a transaction ID equal to the earliest-assigned transaction ID(Tune, [0101 -- At a step 810, the indicator field is examined to detect whether the identifier is unique as discussed above. If, at a step 820, the indicator is unique then (as a “yes” branch 825) control passes (by the bypass path 430) to a step 830 at which the response is issued back towards the initiator.]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Tune into the system of Lai, Kwon for the benefit of an interconnect that significantly allows reduction in latency of write transactions. The interconnect avoids potential deadlock condition(Tune, 0015).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai(2021/0294765), in view of Kwon et al.(20120159037), in view of Richards et al.(2014/0269760), in view of Tune et al.(2019/0266010), and further in view of Kaushik et al.(2022/0222195).
As per claim 11, the system of claim 10 is incorporated, in addition, Lai, Kwon in view of Richards and Tune does not explicitly disclose the following, however Kaushik discloses:
wherein the given transaction ID assignment logic unit is to update a value of the earliest-assigned transaction ID in response to the signal from the shared reorder buffer(Kaushik, [0108 -- At step 448, the ordering circuitry 114 extracts a next transaction ID (e.g., the second transaction ID TI2) from transaction data associated with the first pointer value (e.g., the first transaction data). At step 450, the ordering circuitry 114 updates the first pointer value to the next transaction ID]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Kaushik into the system of Lai, Kwon for the benefit of a system that eliminates various comparison circuits in the transaction ordering system to order various transactions, realizes that size and manufacturing cost of the system-on-chip (SoC) are significantly less than that of an SoC that utilizes counters for ordering transactions and implements different comparison circuits(Kaushik, 0020).
Claim(s) 12-13, 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai(2021/0294765), in view of Kwon et al.(20120159037), and further in view of Tune et al.(2019/0266010).
As per claim 12, the system of claim 1 is incorporated, in addition, Lai does not explicitly disclose the following, however Tune discloses:
wherein the shared reorder buffer is to compare the transaction IDs of the ones of the plurality of memory responses to earliest-assigned transaction IDs of respective memory responses not yet been received by respective processors of the plurality of processors(Tune, [0101 -- At a step 810, the indicator field is examined to detect whether the identifier is unique as discussed above], [0083 -- Referring to FIG. 4, the circuitry 400 receives transactions at a transaction input 410 (also functioning as a response output—to be described below) with their associated indicators. Detection circuitry acting as an indicator detector 420 detects whether the indicator associated with a received transaction request indicates that the identifier is unique as discussed above]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Tune into the system of Lai for the benefit of an interconnect that significantly allows reduction in latency of write transactions. The interconnect avoids potential deadlock condition(Tune, 0015).
As per claim 13, the system of claim 12 is incorporated, in addition, Lai does not explicitly disclose the following, however Tune discloses:
wherein the shared reorder buffer is to send to a given one of the processors, one of the memory responses having one of the transaction IDs matching one of the earliest-assigned transaction IDs of one of the respective memory responses not yet received by the given processor(Tune, [0101 -- At a step 810, the indicator field is examined to detect whether the identifier is unique as discussed above. If, at a step 820, the indicator is unique then (as a “yes” branch 825) control passes (by the bypass path 430) to a step 830 at which the response is issued back towards the initiator.]).
Claim(s) 21 is directed to method steps that are implemented by the system/apparatus claim 12.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai(2021/0294765), and further in view of Kaushik et al.(2022/0222195).
As per claim 14, the system of claim 1 is incorporated, in addition, Lai does not explicitly disclose the following, however Kaushik discloses:
wherein the system is implemented on a single integrated circuit (IC)(Kaushik, [0027 -- FIG. 1 illustrates a schematic block diagram of a system-on-chip (SoC) 100 in accordance with an embodiment of the present disclosure. The SoC 100 includes first and second devices 102a and 102b, an interconnect 104, a third device 106, and a transaction ordering system 108.]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Kaushik into the system of Lai for the benefit of a system that eliminates various comparison circuits in the transaction ordering system to order various transactions, realizes that size and manufacturing cost of the system-on-chip (SoC) are significantly less than that of an SoC that utilizes counters for ordering transactions and implements different comparison circuits(Kaushik, 0020).
As per claim 15, the system of claim 1 is incorporated, in addition, Lai does not explicitly disclose the following, however Kaushik discloses:
wherein the memory requests are input/output (I/O) requests to memory on a same integrated circuit (IC) as the processors(Kaushik, [0027 -- The SoC 100 includes first and second devices 102a and 102b, an interconnect 104, a third device 106, and a transaction ordering system 108. The transaction ordering system 108 includes a storage circuit 110 that is configured to store a transaction table 112, and ordering circuitry 114. In an embodiment, the first and second devices 102a and 102b correspond to Advanced eXtensible Interface (AXI) master devices (e.g., a direct-memory-access controller, a processor, or the like), and the third device 106 corresponds to an AXI slave device (e.g., a memory system, a packet classifier, or the like). ]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Kaushik into the system of Lai for the benefit of a system that eliminates various comparison circuits in the transaction ordering system to order various transactions, realizes that size and manufacturing cost of the system-on-chip (SoC) are significantly less than that of an SoC that utilizes counters for ordering transactions and implements different comparison circuits(Kaushik, 0020).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-21 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Winkler et al.(20040024948) involves a device that has a transmit engine to send upstream commands based on received non-posted read requests from a requestor. A receive engine gets response data in reply to commands previously sent by the transmit engine and sends responses to the requestor. A response reordering mechanism has a unit to control the receive engine to send the responses in correct order, and a buffer to store received response data.
Han(20240385973) involves a device that has a slave interface connected to a direct-current access (DMA) of an NPU, and a master interface connected with a dynamic RAM with multiple slave ports. A switch connects the slave interface and the master interface, where the switch receives a data read request from the DMA of the NPU and transfers the data to the DRAM. A re-order buffer stores the data returned from the slave ports in response to the request. The switch includes a scheduler that reads instruction data required for scheduling from a port, where the switch receives data or response corresponding to received request from the slave ports.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
Prosecution Insights