Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/11/2024 and 5/6/2025 are being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 6 and 10 are objected to because of the following informalities:
In claims 6 and 10, lines 3, 5, and 7, “,” should read -;-.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “low-level” in claim 6 is a relative term which renders the claim indefinite. The term “low-level” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Similar problem exists in claim 10.
The term “high-level” in claim 6 is a relative term which renders the claim indefinite. The term “high-level” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Similar problem exists in claim 10.
In claim 10, line 7, regarding “to enable”, it is not clear whether the capacitor is discharged.
In claim 10, line 9, regarding “to enable”, it is not clear whether the capacitor is charged.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shaik et al. (U.S. Patent No. 11,176,991), hereafter referred to as Shaik’991.
Referring to claim 1, Shaik’991 as claimed, a memory device comprising (see Fig. 3): a plurality of memory cells performing in-memory computing (compute-in-memory (CIM) systems employing CIM circuits employing SRAM bit cells used for multiply-and-accumulate (MAC) operations, see Col. 7, lines 13-42), wherein each of the plurality of memory cells includes a storage unit storing data (the CIM circuits each include SRAM bit cell circuit that includes a storage circuit for storing data, see Col. 7, lines 19-20), and an operation circuit that includes a capacitor and controls a voltage charged to the capacitor according to input data and storage data stored in the storage unit (a capacitor circuit provided and coupled to a multiplication output node of the multiplication circuit in the CIM circuit. The capacitor circuit stores a charge representing the multiplication product output of the multiplication operation of the CIM circuit to be asserted, see Col. 9, lines 32-52).
As to claim 2, Shaik’991 also discloses the storage unit includes SRAM having a 6T structure (a memory bit cell circuit in the form of a 6T SRAM bit cell circuit, see Fig. 3 and Col. 10, lines 13-25) and includes a first inverter and a second inverter, outputs inverted storage data through a first output node to which an output terminal of the second inverter and an input terminal of the first inverter are connected, or outputs the storage data through a second output node to which an output terminal of the first inverter and an input terminal of the second inverter are connected (the 6T SRAM bit cell circuit includes a storage circuit that includes a true inverter circuit and a complement inverter circuit. The true inverter circuit and complement inverter circuit each include respective true and complement PFETS and NFETS, see Fig. 3 and Col. 10, line 39 to Col. 11, line 21).
As to claim 3, Shaik’991 also discloses the operation circuit includes:
a first switching element which is switched according to the input data and has a first terminal connected to a first output node of the storage unit and transmits inverted storage data to a second terminal of the first switching unit (PFETs, NFETS, see Col. 10, lines 39-65; operations on 6T including the gates G of the true and complement PFETs 330T, 330C are configured to receive respective input data signals represented as input data X and XB. The input data XB, X stored at only of the respective true and complement storage nodes 326T, 326C is passed by the respective PFETs 330T, 330C of the XNOR circuit to the multiplication output node 314 at a time, see Col. 10, line 13 to Col. 11, line 52 and Fig. 3); a second switching element which is switched according to the input data and has a first terminal connected to a power supply voltage and transmits the power supply voltage to a second terminal of the second switching element (the supply voltage VDD powering the SRAM bit cell circuit, see Col. 12, line 1-32); and a capacitor having a first terminal connected to the second terminal of the first switching element and to the second terminal of the second switching element, and the input data is applied to a gate of the first switching element and a gate of the second switching element (the CIM circuit also includes a capacitor circuit that is configured to store a charge to latch the multiplication output, see Col. 11, lines 53-63; also note: a capacitor circuit provided and coupled to a multiplication output node of the multiplication circuit in the CIM circuit. The capacitor circuit stores a charge representing the multiplication product output of the multiplication operation of the CIM circuit to be asserted, see Col. 9, lines 32-52).
As to claim 4, Shaik’991 also discloses the first switching element is one of an NMOS transistor and a transmission gate, and the second switching element is a PMOS transistor (PFETs, NFETS, see Col. 10, lines 39-65, Col. 11, lines 26-39, Col. 12, lines 3-20, and Fig. 3).
As to claim 5, Shaik’991 also discloses the operation circuit outputs a NAND operation result of the input data and the storage data (see Figs. 2 and 3; also note: multiplication operation between input data and storage data in the storage circuit of the SRAM bit cell, see Col. 2, lines 39-52, Col. 5, lines 9-56).
As to claim 6, Shaik’991 also discloses when the input data is low-level data, the second switching element is turned on, and the power supply voltage is charged to the capacitor regardless of the storage data (the true and complement PFETs are coupled to a positive supply voltage rail configured to receive a supply voltage VDD. The true inverter circuit has a true inverter node that is configured to receive an input signal to generate an output signal on a true inverter output node of an opposite logic value of the logic value of the input signal…The complement inverter circuit is configured to generate an output signal on its complement inverter output node that has a logic value opposite of the output signal, see Col. 10, line 39 to Col. 13, line 7 and Figs. 3 and 4; also note: pre-charging a bit line and activating an access circuit, see Col. 7, lines 22-24), when the input data is high-level data, the first switching element is turned on, and a voltage charged to the capacitor changes depending on the storage data, when the storage data is low-level data, the first output node outputs high-level data, and a high-level voltage is charged to the capacitor (the CIM circuit also includes a capacitor circuit that is configured to store a charge to latch the multiplication output, see Col. 11, lines 53-63; also note: a capacitor circuit provided and coupled to a multiplication output node of the multiplication circuit in the CIM circuit. The capacitor circuit stores a charge representing the multiplication product output of the multiplication operation of the CIM circuit to be asserted, see Col. 9, lines 32-52), and when the storage data is high-level data, the first output node outputs low-level data, and the capacitor is discharged to be in a low-level voltage (The data stored on the true storage node may be weight data that is multiplied by the input data XB by the multiplication circuit…The multiplication operation in the storage data stored at the true and complement storage nodes is also discharged to the bit line and complement bit line BLB, see Col. 11, lines 43-52; also note: discharging in Col. 12, lines 16-20, 35-60, Col. 18, lines 14-22).
As to claim 7, Shaik’991 also discloses the operation circuit includes: a first switching element which is switched according to inverted input data and has a first terminal that is grounded (ground, see Figs. 3, 4, 7, and 9); a second switching element which is switched according to the inverted input data and has a first terminal connected to a second output node of the storage unit and transmits the storage data to a second terminal of the second switching element (PFETs, NFETS, see Col. 10, lines 39-65; operations on 6T including the gates G of the true and complement PFETs 330T, 330C are configured to receive respective input data signals represented as input data X and XB. The input data XB, X stored at only of the respective true and complement storage nodes 326T, 326C is passed by the respective PFETs 330T, 330C of the XNOR circuit to the multiplication output node 314 at a time, see Col. 10, line 13 to Col. 11, line 52 and Figs. 3, 4, 7, 9); and a capacitor having a first terminal connected to a second terminal of the first switching element and to a second terminal of the second switching element, and the inverted input data is applied to a gate of the first switching element and a gate of the second switching element (the CIM circuit also includes a capacitor circuit that is configured to store a charge to latch the multiplication output, see Col. 11, lines 53-63; also note: a capacitor circuit provided and coupled to a multiplication output node of the multiplication circuit in the CIM circuit. The capacitor circuit stores a charge representing the multiplication product output of the multiplication operation of the CIM circuit to be asserted, see Col. 9, lines 32-52).
Note claim 8 recites similar limitations of claim 4. Therefore it is rejected based on the same reason accordingly.
As to claim 9, Shaik’991 also discloses the operation circuit outputs an AND operation result of the input data and the storage data (see Figs. 2 and 3; also note: multiplication operation between input data and storage data in the storage circuit of the SRAM bit cell, see Col. 2, lines 39-52, Col. 5, lines 9-56).
As to claim 10, Shaik’991 also discloses when the input data is low-level data, the first switching element is turned on and the capacitor is discharged through a ground regardless of the storage data (The data stored on the true storage node may be weight data that is multiplied by the input data XB by the multiplication circuit…The multiplication operation in the storage data stored at the true and complement storage nodes is also discharged to the bit line and complement bit line BLB, see Col. 11, lines 43-52; also note: discharging in Col. 12, lines 16-20, 35-60, Col. 18, lines 14-22), when the input data is high-level data, the second switching element is turned on and a voltage charged to the capacitor changes according to the storage data (the CIM circuit also includes a capacitor circuit that is configured to store a charge to latch the multiplication output, see Col. 11, lines 53-63; also note: a capacitor circuit provided and coupled to a multiplication output node of the multiplication circuit in the CIM circuit. The capacitor circuit stores a charge representing the multiplication product output of the multiplication operation of the CIM circuit to be asserted, see Col. 9, lines 32-52), when the storage data is low-level data, the second output node outputs low-level data to enable the capacitor to be discharged to be in a low-level voltage (The data stored on the true storage node may be weight data that is multiplied by the input data XB by the multiplication circuit…The multiplication operation in the storage data stored at the true and complement storage nodes is also discharged to the bit line and complement bit line BLB, see Col. 11, lines 43-52; also note: discharging in Col. 12, lines 16-20, 35-60, Col. 18, lines 14-22), and when the storage data is high-level data, the second output node outputs high-level data to enable the capacitor to be charged to a high-level voltage (charged and/or pre-charged, see Col. 4, lines 46-62, Col. 7, lines 22-24, Col. 19, lines 33-38, Col. 12, lines 14-60, Col. 15, lines 28-53).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
PENG et al. (U.S. Publication No. 2019/0370640 A1) discloses architecture on in-memory computing memory device for use in artificial neuron.
Yang et al. (U.S. Publication No. 2022/0276835 A1) discloses sub-cell, mac array and bit-width reconfigurable mixed-signal in-memory computing module.
SUMBUL et al. (U.S. Publication No. 2019/0042199 A1) discloses compute in memory circuits with multi-VDD arrays and/or analog multipliers.
Sinangil (U.S. Publication No. 2021/0158854 A1) discloses compute in memory system in which the read bit-lines are isolated from the nodes storing the memory states.
Yang et al. (U.S. Publication No. 2022/0351761 A1) discloses sub-cell, MAC array and bit-width reconfigurable mixed-signal in-memory computing module.
KNAG et al. (U.S. Publication No. 2020/0233923 A1) discloses binary, ternary and bit serial compute-in-memory circuits.
Azuma (U.S. Patent No. 5,325,325) discloses a semiconductor memory device capable of initializing storage data.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
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/TITUS WONG/Primary Examiner, Art Unit 2181
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