DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 22, 2025, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement filed December 11, 2024, fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. The provided copy of JP H11-162771 is partially blank (see, e.g., pages 2-3). It has been placed in the application file, but the information referred to therein has not been considered.
Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Drawings
The drawings were received on December 11, 2024. These drawings are acceptable.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites, “each of the first, second, third, and fourth base electrode layers is defined by a baked layer including a glass component and a metal.”
Claim 2, from which claim 18 depends, recites, “a first base electrode layer and a third base electrode layer defined by sputtered electrodes… a second base electrode layer and a fourth base electrode layer defined by sputtered electrodes”.
It is unclear how the base electrode layers may be defined as both sputtered electrodes and also defined by baked layers containing a glass component and a metal.
A review of the specification provides page 48 paragraph 159, “When Base Electrode Layer is Baked Layer”, and page 49 paragraph 161, “applying the conductive paste… dipping or screen-printing”.
The specification also provides page 49 paragraph 162, “When Base Electrode Layer is Thin Film Layer”, “a thin film forming method such as a sputtering method”.
As these are separate processes forming different types of layers, defining them together as set forth in claim 18 is unclear.
Accordingly, claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
It would appear claim 18 should depend from claim 3 (base layers formed by screen printing). The rejection of claim 18, set forth below, assumes that claim 18 is dependent upon claim 3 (screen printed base layer) and not claim 2 (thin film base layer).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-6, and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent 5,012,388 to Kabeshita et al. (hereinafter Kabeshita).
Claim 1
Kabeshita (FIG. 1-5) discloses a multilayer ceramic electronic component comprising:
a multilayer body (2) including a plurality of stacked ceramic layers (column 2 lines 65-68), a first main surface (top) and a second main surface (bottom) facing each other in a height direction, a first side surface (first side) and a second side surface (second side) facing each other in a width direction orthogonal or substantially orthogonal to a stacking direction of the plurality of ceramic layers, a first end surface (first end) and a second end surface (second end) facing each other in a length direction orthogonal or substantially orthogonal to the stacking direction and the width direction, a first inner electrode layer (column 2 lines 65-68) stacked alternately with the plurality of ceramic layers and exposed on the first end surface (first end), and a second inner electrode layer (column 2 lines 65-68) stacked alternately with the plurality of ceramic layers and exposed on the second end surface (second end);
a first outer electrode (3) extending from the first end surface (first end) of the multilayer body (2) to each of the first main surface (top) and the second main surface (bottom); and
a second outer electrode (3) extending from the second end surface (second end) of the multilayer body (2) to each of the first main surface (top) and the second main surface (bottom); wherein
the first outer electrode (3) includes a first main surface inclined portion (4) extending from a side of the first main surface (top) of the multilayer body (2) to a side of the first end surface (first end); and
the second outer electrode (3) includes a second main surface inclined portion (4) extending from the side of the first main surface (top) of the multilayer body (2) to a side of the second end surface (second end).
Claim 4
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, wherein
the first main surface inclined portion (4) of the first outer electrode (3) covers a ridge portion defined by the first main surface (top) and the first end surface (first end) of the multilayer body (2)(FIG. 1B, the outer electrode 3 covers all of the multilayer body 2 with no ridge of 2 exposed by outer electrode 3); and
the second main surface inclined portion (4) of the second outer electrode (3) covers a ridge portion defined by the first main surface (top) and the second end surface (second end) of the multilayer body (2)(FIG. 1B, the outer electrode 3 covers all of the multilayer body 2 with no ridge of 2 exposed by outer electrode 3).
Claim 5
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, wherein
the first outer electrode (3) includes a third main surface inclined portion (4) extending from a side of the second main surface (bottom) of the multilayer body (2) to the side of the first end surface (first end); and
the second outer electrode (3) includes a fourth main surface inclined portion (4) extending from the side of the second main surface (1a) of the multilayer body (2) to the side of a second end surface (second end).
Claim 6
Kabeshita discloses the multilayer ceramic electronic component according to claim 5, wherein
the third main surface inclined portion (4) of the first outer electrode (3) covers a ridge portion defined by the second main surface (bottom) and the first end surface (first end) of the multilayer body (2)(FIG. 1B, the outer electrode 3 covers all of the multilayer body 2 with no ridge of 2 exposed by outer electrode 3); and
the fourth main surface inclined portion (4) of the second outer electrode (3) covers a ridge portion defined by the second main surface (bottom) and the second end surface (second end) of the multilayer body (2)(FIG. 1B, the outer electrode 3 covers all of the multilayer body 2 with no ridge of 2 exposed by outer electrode 3).
Claim 9
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, wherein
in the first outer electrode (3), an angle between a first main surface exposed portion provided on the first main surface (top) of the multilayer body and the first main surface inclined portion is about 120° or more and about 170° or less (FIG. 1-2, column 3 lines 11-15, note θ is the supplementary angle of the claimed 120° to 170°); and
in the second outer electrode (3), an angle between a second main surface exposed portion provided on the first main surface (top) of the multilayer body and the second main surface inclined portion is about 120° or more and about 170° or less (FIG. 1-2, column 3 lines 11-15, note θ is the supplementary angle of the claimed 120° to 170°).
Claim 10
Kabeshita discloses the multilayer ceramic electronic component according to claim 5, wherein
in the first outer electrode (3), an angle between a third main surface exposed portion provided on the second main surface (bottom) of the multilayer body and the third main surface inclined portion is about 120° or more and about 170° or less (FIG. 1-2, column 3 lines 11-15, note θ is the supplementary angle of the claimed 120° to 170°); and
in the second outer electrode (3), an angle between a fourth main surface exposed portion provided on the second main surface (bottom) of the multilayer body and the fourth main surface inclined portion is about 120° or more and about 170° or less (FIG. 1-2, column 3 lines 11-15, note θ is the supplementary angle of the claimed 120° to 170°).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kabeshita in view of US Publication 2021/0327649 to Muramatsu et al. (hereinafter Muramatsu).
Claim 2
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein the first outer electrode includes a first base electrode layer and a third base electrode layer defined by sputtered electrodes, and a first end surface plated layer; the second outer electrode includes a second base electrode layer and a fourth base electrode layer defined by sputtered electrodes, and a second end surface plated layer; the first base electrode layer covers a portion of the first main surface on the side of the first end surface of the multilayer body; the second base electrode layer covers a portion of the first main surface on the side of the second end surface of the multilayer body; the third base electrode layer covers a portion of the second main surface on the side of the first end surface of the multilayer body; the fourth base electrode layer covers a portion of the second main surface on the side of the second end surface of the multilayer body; the first end surface plated layer is provided on the first end surface and covers a region including the first inner electrode layer exposed on the first end surface and the first base electrode layer and the third base electrode layer; and the second end surface plated layer is provided on the second end surface and covers a region including the second inner electrode layer exposed on the second end surface and the second base electrode layer and the fourth base electrode layer, as recited in claim 2.
Muramatsu (FIG. 4-6) teaches wherein a first outer electrode (24) includes a first base electrode layer (26a1) and a third base electrode layer (26a2) defined by sputtered electrodes (paragraph 80), and a first end surface plated layer (28a); a second outer electrode includes a second base electrode layer (26b1) and a fourth base electrode layer (26b2) defined by sputtered electrodes, and a second end surface plated layer (28b); the first base electrode layer (26a1) covers a portion of a first main surface (12a) on a side of a first end surface (12e) of a multilayer body (12); the second base electrode layer (26b1) covers a portion of the first main surface (12a) on a side of a second end surface (12f) of the multilayer body (12); the third base electrode layer (26a2) covers a portion of a second main surface (12b) on a side of the first end surface (12e) of the multilayer body (12); the fourth base electrode layer (26b2) covers a portion of the second main surface (12b) on a side of the second end surface (12f) of the multilayer body (12); the first end surface plated layer (28a) is provided on the first end surface (12e) and covers a region including a first inner electrode layer (20a) exposed on the first end surface (12e) and the first base electrode layer (26a1) and the third base electrode layer (26a2); and the second end surface plated layer (28b) is provided on the second end surface (12f) and covers a region including a second inner electrode layer (20b) exposed on the second end surface (12f) and the second base electrode layer (26b1) and the fourth base electrode layer (26b2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Muramatsu with Kabeshita to incorporate external electrode structure as taught by Muramatsu in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for an evenly formed and thin base layer with increased performance (Muramatsu paragraph 77), while avoiding deterioration or penetration of the base electrode by a plating solution (paragraph 90).
Claim 12
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein each of the plurality of ceramic layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component, as recited in claim 12.
Muramatsu (paragraph 51) teaches wherein each of a plurality of ceramic layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Muramatsu with Kabeshita to incorporate ceramic materials as taught by Muramatsu in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for perovskite materials with high dielectric constants and volumetric efficiency.
Claim 13
Kabeshita with Muramatsu teaches the multilayer ceramic electronic component according to claim 12, wherein each of the plurality of ceramic layers includes a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound as a subcomponent (Muramatsu paragraph 51).
Claim 14
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein a thickness of each of the plurality of ceramic layers is about 0.4 μm or more and about 5.0 μm or less, as recited in claim 14.
Muramatsu (paragraph 50) teaches wherein a thickness of each of a plurality of ceramic layers is about 0.4 μm or more and about 5.0 μm or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Muramatsu with Kabeshita to incorporate ceramic material thickness as taught by Muramatsu in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for using a high number of layers within the multilayer ceramic component, increasing capacitance.
Claim 15
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein a number of the plurality of ceramic layers is 10 or more and 700 or less, as recited in claim 15.
Muramatsu (paragraph 50) teaches wherein a number of a plurality of ceramic layers is 10 or more and 700 or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Muramatsu with Kabeshita to incorporate a number of ceramic layers as taught by Muramatsu in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for using a high number of layers within the multilayer ceramic component, increasing capacitance.
Claim 16
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein each of the first and second inner electrode layers includes Ni, Cu, Ag, Pd, or Au, or an alloy including at least one of Ni, Cu, Ag, Pd, or Au, as recited in claim 16.
Muramatsu (paragraph 64) teaches wherein each of a first and second inner electrode layers includes Ni, Cu, Ag, Pd, or Au, or an alloy including at least one of Ni, Cu, Ag, Pd, or Au.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Muramatsu with Kabeshita to incorporate internal electrode layer materials as taught by Muramatsu in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for selecting a material based on cost, conductivity, grain size, temperature performance, and other characteristics.
Claim 17
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein a thickness of each of the first and second inner electrode layers is about 0.2 µm or more and about 2.0 µm or less, as recited in claim 17.
Muramatsu (paragraph 69) teaches wherein a thickness of each of a first and second inner electrode layers is about 0.2 µm or more and about 2.0 µm or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Muramatsu with Kabeshita to incorporate inner conductive layer thickness as taught by Muramatsu in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for using a high number of layers within the multilayer ceramic component, increasing capacitance.
Claim 3, 12-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kabeshita in view of US Publication 2022/0392709 to Nakahiro et al. (hereinafter Nakahiro).
Claim 3
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein the first outer electrode includes a first base electrode layer and a third base electrode layer which are screen-printed, and a first end surface electrode; the second outer electrode includes a second base electrode layer and a fourth base electrode layer, which are screen-printed, and a second end surface electrode; the first base electrode layer covers a portion of the first main surface on the side of the first end surface of the multilayer body; the second base electrode layer covers a portion of the first main surface on the side of the second end surface of the multilayer body; the third base electrode layer covers a portion of the second main surface on the side of the first end surface of the multilayer body; the fourth base electrode layer covers a portion of the second main surface on the side of the second end surface of the multilayer body; the first end surface electrode is provided on a surface of the first end surface, and covers a portion of the first base electrode layer and a portion of the third base electrode layer; and the second end surface electrode is provided on a surface of the second end surface, and covers a portion of the second base electrode layer and a portion of the fourth base electrode layer, as recited in claim 3.
Nakahiro (FIG. 5C) teaches wherein a first outer electrode (40a) includes a first base electrode layer (50A) and a third base electrode layer (50A) which are screen-printed (paragraph 205), and a first end surface electrode (60A); a second outer electrode (40b) includes a second base electrode layer (50B) and a fourth base electrode layer (50B), which are screen-printed (paragraph 205), and a second end surface electrode (60B); the first base electrode layer (50A) covers a portion of a first main surface (TS2) on a side of a first end surface (LS1) of a multilayer body (10); the second base electrode layer (50B) covers a portion of the first main surface (TS2) on a side of a second end surface (LS2) of the multilayer body (10); the third base electrode layer (50A) covers a portion of the second main surface (TS1) on a side of the first end surface (LS1) of the multilayer body (10); the fourth base electrode layer (50B) covers a portion of the second main surface (TS1) on a side of the second end surface (LS2) of the multilayer body (10); the first end surface electrode (60A) is provided on a surface of the first end surface (LS1), and covers a portion of the first base electrode layer (50A) and a portion of the third base electrode layer (50A); and the second end surface electrode (60B) is provided on a surface of the second end surface (LS2), and covers a portion of the second base electrode layer (50B) and a portion of the fourth base electrode layer (50B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Nakahiro with Kabeshita to incorporate external electrode structure as taught by Nakahiro in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for use of metal and ceramic components in the base electrode layer (Nakahiro paragraph 205), allowing for a better thermal expansion match with the multilayer body.
Claim 12
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein each of the plurality of ceramic layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component, as recited in claim 12.
Nakahiro (paragraph 53) teaches wherein each of a plurality of ceramic layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Nakahiro with Kabeshita to incorporate ceramic materials as taught by Nakahiro in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for perovskite materials with high dielectric constants and volumetric efficiency.
Claim 13
Kabeshita with Nakahiro teaches the multilayer ceramic electronic component according to claim 12, wherein each of the plurality of ceramic layers includes a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound as a subcomponent (Nakahiro paragraph 53).
Claim 14
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein a thickness of each of the plurality of ceramic layers is about 0.4 μm or more and about 5.0 μm or less, as recited in claim 14.
Nakahiro (paragraph 54) teaches wherein a thickness of each of a plurality of ceramic layers is about 0.4 μm or more and about 5.0 μm or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Nakahiro with Kabeshita to incorporate ceramic material thickness as taught by Nakahiro in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for using a high number of layers within the multilayer ceramic component, increasing capacitance.
Claim 15
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein a number of the plurality of ceramic layers is 10 or more and 700 or less, as recited in claim 15.
Nakahiro (paragraph 54) teaches wherein a number of a plurality of ceramic layers is 10 or more and 700 or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Nakahiro with Kabeshita to incorporate a number of ceramic layers as taught by Nakahiro in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for using a high number of layers within the multilayer ceramic component, increasing capacitance.
Claim 16
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein each of the first and second inner electrode layers includes Ni, Cu, Ag, Pd, or Au, or an alloy including at least one of Ni, Cu, Ag, Pd, or Au, as recited in claim 16.
Nakahiro (paragraph 61) teaches wherein each of a first and second inner electrode layers includes Ni, Cu, Ag, Pd, or Au, or an alloy including at least one of Ni, Cu, Ag, Pd, or Au.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Nakahiro with Kabeshita to incorporate internal electrode layer materials as taught by Nakahiro in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for selecting a material based on cost, conductivity, grain size, temperature performance, and other characteristics.
Claim 17
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein a thickness of each of the first and second inner electrode layers is about 0.2 µm or more and about 2.0 µm or less, as recited in claim 17.
Nakahiro (paragraph 62) teaches wherein a thickness of each of a first and second inner electrode layers is about 0.2 µm or more and about 2.0 µm or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Nakahiro with Kabeshita to incorporate inner conductive layer thickness as taught by Nakahiro in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for using a high number of layers within the multilayer ceramic component, increasing capacitance.
Claim 18
Kabeshita with Nakahiro teaches the multilayer ceramic electronic component according to claim 3 (not claim 2, see rejection of claim 18 under 35 USC 112b, above), wherein each of the first, second, third, and fourth base electrode layers is defined by a baked layer (Nakahiro 50A-B, 60A-B) including a glass component and a metal (paragraph 81).
Claim 20
Kabeshita with Nakahiro teaches the multilayer ceramic electronic component according to claim 18, wherein the metal includes at least one of Cu, Ni, Ag, Pd, an Ag—Pd alloy, or Au (Nakahiro paragraph 78).
Claims 7-8 and 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kabeshita in view of JP Publication 2016-86063 to Kato et al. (hereinafter Kato; see also provided machine translation).
Claim 7
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein the first outer electrode includes: a first side surface inclined portion extending from the side of the first main surface of the multilayer body to a side of the first side surface; a second side surface inclined portion extending from the side of the first main surface of the multilayer body to a side of the second side surface; a third side surface inclined portion extending from a side of the second main surface of the multilayer body to the side of the first side surface; and a fourth side surface inclined portion extending from the side of the second main surface of the multilayer body to the side of the second side surface; and the second outer electrode includes: a fifth side surface inclined portion extending from the side of the first main surface of the multilayer body to the side of the first side surface; a sixth side surface inclined portion extending from the side of the first main surface of the multilayer body to the side of the second side surface; a seventh side surface inclined portion extending from the side of the second main surface of the multilayer body to the side of the first side surface; and an eighth side surface inclined portion extending from the side of the second main surface of the multilayer body to the side of the second side surface, as recited in claim 7.
Kato (FIG. 1-2) teaches wherein a first outer electrode (3a) includes a first side surface inclined portion (6) extending from a side of a first main surface (1b) of a multilayer body (10) to a side of a first side surface (1e); a second side surface inclined portion (6) extending from a side of the first main surface (1b) of the multilayer body (10) to a side of a second side surface (1f); a third side surface inclined portion extending (6) from a side of a second main surface (1a) of the multilayer body (10) to a side of a first side surface (1e); and a fourth side surface inclined (6) portion extending from a side of the second main surface (1a) of the multilayer body (10) to a side of the second side surface (1f); and a second outer electrode (3b) includes a fifth side surface inclined portion (6) extending from the side of the first main surface (1b) of the multilayer body (10) to the side of the first side surface (1e); a sixth side surface inclined portion (6) extending from the side of the first main surface (1b) of the multilayer body (10) to the side of the second side surface (1f); a seventh side surface inclined portion (6) extending from the side of the second main surface (1a) of the multilayer body (10) to the side of the first side surface (1e); and an eighth side surface inclined portion (6) extending from the side of the second main surface (1a) of the multilayer body (10) to the side of the second side surface (1f).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Kato with Kabeshita to incorporate the ridge line portions of Kato in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for reduction of stress concentration and chipping.
Claim 8
Kabeshita with Kato teaches the multilayer ceramic electronic component according to claim 7, wherein
in the first outer electrode (Kato 3):
the first side surface inclined portion (6) covers a ridge portion defined by the first main surface (1b) and the first side surface (1e) of the multilayer body (10);
the second side surface inclined portion (6) covers a ridge portion defined by the first main surface (1b) and the second side surface (1f) of the multilayer body (10);
the third side surface inclined portion (6) covers a ridge portion defined by the second main surface (1b) and the first side surface (1e) of the multilayer body (10); and
the fourth side surface inclined portion (6) covers a ridge portion defined by the second main surface (1b) and the second side surface (1f) of the multilayer body (10); and
in the second outer electrode:
the fifth side surface inclined portion (6) covers a ridge portion defined by the first main surface (1b) and the first side surface (1e) of the multilayer body (10);
the sixth side surface inclined portion (6) covers a ridge portion defined by the first main surface (1b) and the second side surface (1f) of the multilayer body (10);
the seventh side surface inclined portion (6) covers a ridge portion defined by the second main surface (1b) and the first side surface (1e) of the multilayer body (10); and
the eighth side surface inclined portion (6) covers a ridge portion defined by the second main surface (1b) and the second side surface (1f) of the multilayer body (10)(Kato FIG. 1-2).
Claim 12
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein each of the plurality of ceramic layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component, as recited in claim 12.
Kato (paragraph 19, 75) teaches wherein each of a plurality of ceramic layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Kato with Kabeshita to incorporate ceramic materials as taught by Kato in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for perovskite materials with high dielectric constants and volumetric efficiency.
Claim 13
Kabeshita with Kato teaches the multilayer ceramic electronic component according to claim 12, wherein each of the plurality of ceramic layers includes a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound as a subcomponent (Kato paragraph 75).
Claim 14
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein a thickness of each of the plurality of ceramic layers is about 0.4 μm or more and about 5.0 μm or less, as recited in claim 14.
Kato (paragraph 18) teaches wherein a thickness of each of a plurality of ceramic layers is about 0.4 μm or more and about 5.0 μm or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Kato with Kabeshita to incorporate ceramic material thickness as taught by Kato in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for using a high number of layers within the multilayer ceramic component, increasing capacitance.
Claim 15
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein a number of the plurality of ceramic layers is 10 or more and 700 or less, as recited in claim 15.
Kato (paragraph 18) teaches wherein a number of a plurality of ceramic layers is 10 or more and 700 or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Kato with Kabeshita to incorporate a number of ceramic layers as taught by Kato in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for using a high number of layers within the multilayer ceramic component, increasing capacitance.
Claim 16
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly wherein each of the first and second inner electrode layers includes Ni, Cu, Ag, Pd, or Au, or an alloy including at least one of Ni, Cu, Ag, Pd, or Au, as recited in claim 16.
Kato (paragraph 23) teaches wherein each of a first and second inner electrode layers includes Ni, Cu, Ag, Pd, or Au, or an alloy including at least one of Ni, Cu, Ag, Pd, or Au.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Kato with Kabeshita to incorporate internal electrode layer materials as taught by Kato in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for selecting a material based on cost, conductivity, grain size, temperature performance, and other characteristics.
Claim 17
Kabeshita discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Kabeshita does not expressly disclose wherein a thickness of each of the first and second inner electrode layers is about 0.2 µm or more and about 2.0 µm or less, as recited in claim 17.
Kato (paragraph 23) teaches wherein a thickness of each of a first and second inner electrode layers is about 0.2 µm or more and about 2.0 µm or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Kato with Kabeshita to incorporate inner conductive layer thickness as taught by Kato in the structure taught by Kabeshita, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for using a high number of layers within the multilayer ceramic component, increasing capacitance.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kabeshita with Nakahiro in view of US Publication 2017/0294268 to Katsuta et al. (hereinafter Katsuta).
Kabeshita with Nakahiro teaches the multilayer ceramic electronic component according to claim 18, as shown above.
Nakahiro does not expressly disclose wherein the glass component includes at least one of B, Si, Ba, Mg, Al, or Li, as recited in claim 19.
Katsuta (paragraph 35) teaches wherein a glass component includes at least one of B, Si, Ba, Mg, Al, or Li.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Katsuta with Kabeshita with Nakahiro to incorporate a glass in a base layer as taught by Katsuta in the structure taught by Kabeshita with Nakahiro, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for a low resistance connection to the internal electrodes while avoiding cracking from thermal expansion mismatch.
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. See and compare, e.g., JP Publication 2019/186295 FIG. 6-7 with application FIG. 12-13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US Publication 2003/0222335 (see, e.g., FIG. 1A).
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/NATHAN MILAKOVICH/Primary Examiner, Art Unit 2847
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