Detailed Action
Status of Claims
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Claims 1-20 are rejected.
This Action is Non-Final.
Claim Objections
5. Claim 2-13 objected to because of the following informalities:
i. Claims 2-12 are objected because, the dependent claims 2-12 comprising “the system” on the preamble but “the system” is not defined previously and it’s not clear which system it’s referring too. It’s requested to be corrected as a “digital communication system…”.
ii. Independent Claim 13 is objected because, it’s required to be written as an independent form by incorporation the limitation of claim 1. Appropriate correction is required.
Information Disclosure Statement
6. The information disclosure statement (IDS) submitted on 12/11/2024, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1 and 6-12 are rejected under 35 U.S.C. 103 as being unpatentable over POEZART et al. (US Patent Application Pub. No: 20200104270 A1) in view Fujita et al.(US Patent Application Pub.No:20020191723 A1).
As per claim 1,POEZART teaches a digital communication system [Fig.4, a communication system 400.], comprising:
a processing device [Fig.5, a processing unit 517.];
a remote device [Fig.5, remote sensors.];
a signal path comprising one or more components and configured to provide a communicative connection between the processing device and the remote device [Paragraphs 0005; 0016, …a digital serial bus; —a master device and at least one slave device operatively connected to said bus in a manner such that each device can receive bit signals from the bus, and such that each device can send dominant bit signals or non-dominant bit signals;….]; and
at least one temperature sensor configured to sense a temperature and send a sensed temperature value to the processing device [Paragraphs 0068;0145,…, the slave device further comprises a sensor unit adapted for measuring a physical quantity at moments in time unrelated to a timing of the bus-interface part, and for providing measurement data indicative of the measured physical quantity; —and wherein the readout unit and/or the processing unit unit comprises a memory and/or a buffer for storing the measurement data provided by the sensor unit.];
wherein: the processing device is configured to generate a clock signal and send the clock signal through the signal path to the remote device [Paragraph 0149,… the processing unit 817 is calculating new values independently of the master clock. Thus, the readout circuit 813 decouples the clock domains.];
the remote device is configured to generate a digital data signal with a timing [Paragraphs 0017;0052;0068,…system that the master can impose the timing of the communication on the data bus.], based on the clock signal and send the digital data signal through the signal path to the processing device [Paragraph 0149,… the processing unit 817 is calculating new values independently of the master clock. Thus, the readout circuit 813 decouples the clock domains.]; and
Poezart does not explicitly disclose the processing device is further configured to derive a delay value from the sensed temperature value, the delay value corresponding to a temperature dependent variation in signal propagation delay along the signal path in both directions, obtain a variable clock signal having a variable delay relative to the clock signal, the variable delay corresponding to the delay value, and use the variable clock signal to sample the digital data signal.
Fujita discloses the processing device is further configured to derive a delay value from the sensed temperature value, the delay value corresponding to a temperature dependent variation in signal propagation delay along the signal path in both directions [Paragraphs 0126-0127, That is, each of the phase comparing delay circuits 30-1 to 30-n is coupled to a temperature sensor unit 70-1 to 70-n which compensates for the temperature dependability of the voltage signal (containing phase comparing information). Each temperature sensor unit 70-1 to 70-n is capable of compensating for a temperature-deriving component of the phase difference .delta. of the voltage signal supplied from the phase comparing circuit 31 in each of the phase comparing delay circuits 30-1 to 30-n.], obtain a variable clock signal having a variable delay relative to the clock signal, the variable delay corresponding to the delay value, and use the variable clock signal to sample the digital data signal [Paragraphs 0007-0009, The phase comparator 102 is a component for comparing the clock CK1 outputted from the phase locked oscillator 104 provided on the downstream stage with the data signal DT in phase and outputting a signal corresponding to the phase difference. The variable delay circuit 103 is a component for effecting delay on the clock N-divided by the N-frequency dividing circuit 101 so that the frequency divided clock becomes synchronized with the data signal DT.].
It would have been obvious one ordinary skill in the art before the effective filling date of the claimed invention, to include Fujita‘s digital communication system into POEZART’s communication system for the benefit of suppresses the increase in size of circuit and hence cost, even when circuit handles large number of parallel data signal lines (Fujita,[0015]) to obtain the invention as specified in claim 1.
As per claim 6, POEZART and Fujita teach all the limitations of claim 1 above, where POEZART and Fujita teach, a system [POEZART, Fig.4, a communication system 400.], wherein the temperature sensor is configured to sense a temperature of the digital communication system or an ambient temperature around the digital communication system [Fujita, Paragraphs 0126-0127, …That is, the temperature sensor unit 70-1 to 70-n detects a change of temperature, and the output voltage signal from the phase comparing circuit 31 is controlled in accordance with the result of temperature detection by using a circuit element such as a resistor, not shown, so that the temperature dependability is compensated for.].
As per claim 7, POEZART and Fujita teach all the limitations of claim 1 above, where POEZART and Fujita teach, a system [POEZART , Fig.4, a communication system 400.], wherein the processing device is configured to derive the delay value from the sensed temperature value using a look up table [Fujita, Paragraphs 0126-0127, That is, each of the phase comparing delay circuits 30-1 to 30-n is coupled to a temperature sensor unit 70-1 to 70-n which compensates for the temperature dependability of the voltage signal (containing phase comparing information). Each temperature sensor unit 70-1 to 70-n is capable of compensating for a temperature-deriving component of the phase difference .delta. of the voltage signal supplied from the phase comparing circuit 31 in each of the phase comparing delay circuits 30-1 to 30-n.].
As per claim 8, POEZART and Fujita teach all the limitations of claim 7 above, where P POEZART and Fujita teach, a system [POEZART, Fig.4, a communication system 400.], wherein the look up table is comprised in the processing device [Fujita, Paragraphs 0126-0127, That is, each of the phase comparing delay circuits 30-1 to 30-n is coupled to a temperature sensor unit 70-1 to 70-n which compensates for the temperature dependability of the voltage signal (containing phase comparing information). Each temperature sensor unit 70-1 to 70-n is capable of compensating for a temperature-deriving component of the phase difference .delta. of the voltage signal supplied from the phase comparing circuit 31 in each of the phase comparing delay circuits 30-1 to 30-n.].
As per claim 9, POEZART and Fujita teach all the limitations of claim 1 above, where POEZART and Fujita teach, a system [POEZART, Fig.4, a communication system 400.], wherein the processing device is configured to generate the variable clock signal by passing the clock signal through a variable delay device [Fujita, Paragraphs 0007-0009, The phase comparator 102 is a component for comparing the clock CK1 outputted from the phase locked oscillator 104 provided on the downstream stage with the data signal DT in phase and outputting a signal corresponding to the phase difference. The variable delay circuit 103 is a component for effecting delay on the clock N-divided by the N-frequency dividing circuit 101 so that the frequency divided clock becomes synchronized with the data signal DT.].
As per claim 10, POEZART and Fujita teach all the limitations of claim 9 above, where POEZART and Fujita teach, a system [POEZART, Fig.4, a communication system 400.], wherein the variable delay device is comprised in the processing device [Fujita, Paragraphs 0007-0009, The phase comparator 102 is a component for comparing the clock CK1 outputted from the phase locked oscillator 104 provided on the downstream stage with the data signal DT in phase and outputting a signal corresponding to the phase difference. The variable delay circuit 103 is a component for effecting delay on the clock N-divided by the N-frequency dividing circuit 101 so that the frequency divided clock becomes synchronized with the data signal DT.].
As per claim 11, POEZART and Fujita teach all the limitations of claim 1 above, where POEZART teaches, a system [POEZART, Fig.4, a communication system 400.], wherein the processing device is a Field Programmable Gate Array (FPGA) [POEZART, Paragraph 0001, … the field of communication systems comprising of master and at least one slave.].
As per claim 12, POEZART and Fujita teach all the limitations of claim 1 above, where POEZART teaches, a system [POEZART, Fig.4, a communication system 400.], wherein the remote device is an analog to digital converter [POEZART, Paragraph 0073,… stored after analog-to-digital conversion or format conversion based on the last value alone, and for example provided as such to the bus-interface part.].
8. Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Poezart et al. (US Patent Application Pub. No: 20200104270 A1) in view Fujita et al.(US Patent Application Pub.No:20020191723 A1), and in view of Mogensen et al.(US Patent. No: 11,341,081 B1).
As per claim 2, POEZART teaches all the limitations of claim 1 above, where POEZART teaches, a system [POEZART, Fig.4, a communication system 400.].
POEZART does not explicitly disclose wherein the digital communication system is configured to use a Serial Peripheral Interface (SPI) digital communication protocol.
However, Mogensen discloses wherein the digital communication system is configured to use a Serial Peripheral Interface (SPI) digital communication protocol [Mogensen, Fig.1A; col.3, ll. 1-11, FIG. 1A is an SPI system 100 according to various examples herein. SPI system 100 includes an SPI Host 102 and an SPI Client 104.].
It would have been obvious one ordinary skill in the art before the effective filling date of the claimed invention, to include Mogensen ‘s method for receiving a chip select signal at a serial peripheral interface (SPI) client device into POEZART’s communication system for the benefit of enables transmitting the first bit of an SPI transmission to an SPI host device with the delay based on a loop propagation delay of an SPI channel in an effective manner (Mogensen,col.4, ll.13-22) to obtain the invention as specified in claim 2.
As per claim 3, POEZART teaches all the limitations of claim 2 above, where POEZART teaches, a system [POEZART, Fig.4, a communication system 400.].
POEZART does not explicitly disclose wherein the digital data signal is a Main In Sub Out (MISO) signal.
However, Mogensen discloses wherein the digital data signal is a Main In Sub Out (MISO) signal [Mogensen,col.4,ll.56-67, Waveform 156 is an example of a MISO signal transmitted on MISO 114.].
It would have been obvious one ordinary skill in the art before the effective filling date of the claimed invention, to include Mogensen ‘s method for receiving a chip select signal at a serial peripheral interface (SPI) client device into POEZART’s communication system for the benefit of enables transmitting the first bit of an SPI transmission to an SPI host device with the delay based on a loop propagation delay of an SPI channel in an effective manner (Mogensen,col.4, ll.13-22) to obtain the invention as specified in claim 3.
As per claim 4, POEZART teaches all the limitations of claim 2 above, where POEZART teaches, a system [POEZART, Fig.4, a communication system 400.].
POEZART does not explicitly disclose wherein the processing device is further configured to generate a Chip Select (CS) signal and send the CS signal through the signal path to the remote device.
However, Mogensen discloses wherein the processing device is further configured to generate a Chip Select (CS) signal and send the CS signal through the signal path to the remote device [Mogensen, col.6, ll.54-60, SPI Client sends the first bit of the eight bits to SPI Host 102 when CS 108 goes low, and then sends the last seven bits of the 8-bit transmission on the first seven clock cycles on SCLK 110.].
It would have been obvious one ordinary skill in the art before the effective filling date of the claimed invention, to include Mogensen ‘s method for receiving a chip select signal at a serial peripheral interface (SPI) client device into POEZART’s communication system for the benefit of enables transmitting the first bit of an SPI transmission to an SPI host device with the delay based on a loop propagation delay of an SPI channel in an effective manner (Mogensen,col.4, ll.13-22) to obtain the invention as specified in claim 4.
As per claim 5, POEZART teaches all the limitations of claim 2 above, where POEZART teaches, a system [POEZART, Fig.4, a communication system 400.].
POEZART does not explicitly disclose wherein the processing device is further configured to generate a Main Out Sub In (MOSI) signal and send the MOSI signal through the signal path to the remote device.
However, Mogensen discloses wherein the processing device is further configured to generate a Main Out Sub In (MOSI) signal and send the MOSI signal through the signal path to the remote device [Mogensen,col.3,ll.47-52, MISO 114 is the data line used to send data from SPI Client 104 to SPI Host 102. MISO 114 connects a MISO pin on SPI Host 102 to a MISO pin on SPI Client 104.].
It would have been obvious one ordinary skill in the art before the effective filling date of the claimed invention, to include Mogensen ‘s method for receiving a chip select signal at a serial peripheral interface (SPI) client device into POEZART’s communication system for the benefit of enables transmitting the first bit of an SPI transmission to an SPI host device with the delay based on a loop propagation delay of an SPI channel in an effective manner (Mogensen,col.4, ll.13-22) to obtain the invention as specified in claim 3.
As per claim 12, claim 13 is rejected in accordance to the same rational and reasoning as the above claim 1, wherein claim 13 is the device claim for the system of claim 1.
As per claims 14-20, claims 14-2 are rejected in accordance to the same rational and reasoning as the above claims 1-9, wherein claims 14-20 are the method claims for the system of claims 1-9.
Conclusion
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
References Considered Pertinent but not relied upon
McGibney et al. (US Patent Application Pub. No: 20230238976 A1) teaches a confined data communication system includes a reference generation circuit operable to produce one or more analog reference signals, an analog to digital converter circuit operable to process an analog signal to produce a digital representative signal, a digital filtering circuit operable to filter the digital representative signal to produce an affect value, a data processing module operable to interpret the affect value to produce processed output data, and a processing module operable to set frequency and waveform for each of the one or more analog reference signals, set digital filtering parameters for the digital filtering circuit, set a sampling rate for the analog to digital converter circuit, and set data interpretation parameters for the data processing module.
Chopperla (US Patent Application Pub. No: 20230143302 A1) teaches a hybrid mode system containing an external device and a field-programmable gate array (“FPGA”) capable of providing configuration data to FPGA via a hybrid communication channel is disclosed. Chopperla discloses the system is able to identify a first communication protocol in accordance with at least a portion of address bits presented on a serial data line (“SDA”) wherein SDA is used as a connection between FPGA and the external device. Chopperla suggests the clock signals for receiving data are adjusted to a first clock frequency in accordance with the first communication protocol and clock cycles presented on a serial clock line (“SCL”). SCL is used to connection between FPGA and the external device; and after transmitting the configuration data, a portion of FPGA is programmed to perform user-defined logic functions in response to the configuration data.
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/GETENTE A YIMER/Primary Examiner, Art Unit 2181
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