DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 11, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "receiving a clock signal and a command/address signal from a memory controller" in line 3. There is insufficient antecedent basis for this limitation in the claim. It is unclear to the Examiner as to what entity is receiving the clock signal and command/address signal from the memory controller.
Claim 11 recites the limitation “transmitting the command/address signal and the clock signal for the second memory chip to the second memory chip”. There is insufficient antecedent basis for this limitation in the claim. No “command/address signal and the clock signal for the second memory chip” has been previously claimed.
Claims 10 and 12-17 are rejected as being dependent upon and thus incorporating therein the rejected subject matter of the respective parent claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 9 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Weingarten (US# 2012/0066441).
Regarding claim 9, Weingarten teaches an operating method of a memory device, the memory device comprising an interface circuit (100) and a plurality of memory chips [within flash (50)], the operating method comprising: receiving a clock signal [although not explicitly recited, a flash memory inherently requires a clock signal to synchronize data transfer between a host and memory] and a command/address signal [0036]from a memory controller; reading some data of a second memory chip from among the plurality of memory chips in advance while reading data of a first memory chip from among the plurality of memory chips based on the command/address signal [simultaneous reading of memories, 0069, lines 4-13]; and storing the read some data of the second memory chip in the interface circuit [read data is temporarily stored in at least hardware 60, 70, 80; Fig. 1A, 0119].
Regarding claim 11, Weingarten teaches transmitting the command/address signal and the clock signal for the second memory chip to the second memory chip in advance while reading the data of the first memory chip [0069; simultaneous reading of memory chips inherently requires clock and command/address signals, which based on the molecular composition of the materials involved (latency based on materials) are considered to occur simultaneously but would technically occur nearly imperceptibly at different times].
Allowable Subject Matter
Claims 1-8 and 18-20 are allowed over the prior art of record
Claims 10 and 12-17 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ning teaches simultaneous test reading on flash chips.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Brian R. Peugh whose telephone number is (571) 272-4199. The examiner can normally be reached on Monday-Friday from 7:30am to 3:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Rocio Del Mar Perez-Velez, phone number 571-270-5935, can be reached. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is 571-272-2100.
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/BRIAN R PEUGH/Primary Examiner, Art Unit 2133