Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are now pending in the application under prosecution and have been examined.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented.
The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features.
Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20220019502 (MYLAVARAPU) .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
With respect to claim 1, MYLAVARAPU teaches memory sub-system (a memory device of a memory sub-system) comprising: a memory device configured as primary memory (first-type memory devices of a memory sub-system, the memory sub-system comprising a set of second-type memory devices) [Fig. 1; Par. 0017-0018]; an ultra-high endurance storage class memory device (non-volatile memory devices comprises a three-dimensional cross-point memory device) [Fig. 1; Par. 0018-0020; Par. 0009]; and a processing device, operatively coupled with the memory device and the ultra-high endurance storage class memory device, to perform operations (memory devices including media controller/processing logic that operate to execute operations on one or more memory cells of the memory devices (e.g., perform media management operations on the memory device)) [Par. 0041-0043; Par. 0035-0036] comprising: generating a set of media management data associated with the memory device (memory sub-system to initiate media management operations (read and write access operations)) [Par. 0040-0042]; and causing the set of media management data to be stored in the ultra-high endurance storage class memory device (causing a portion of management data to be copied from at least one second-type memory device, in the set of second-type memory devices, to at least one third-type memory device in the set of third-type memory devices, the portion of the management data being associated with the individual block) [Par. 0015; Par. 0047; Par. 0055].
With respect to claim 3, MYLAVARAPU teaches memory sub-system, wherein the set of media management data comprises a first subset of tables and a second subset of journals and logs (initiated media management data comprising a set of tables (e.g., logical-to-physical address mapping table), data from logging, scratch pad data) [Par. 0011-0012; Par. 0036-0037].
With respect to claim 3, MYLAVARAPU teaches memory sub-system, wherein the first subset of tables comprises one or more logical-to-physical (L2P) address mapping tables (set of tables including logical-to-physical address mapping table) [Par. 0011-0012].
With respect to claim 4, MYLAVARAPU teaches memory sub-system, the operations further comprising updating at least a portion of the one or more L2P address mapping tables stored in the ultra-high endurance storage class memory device (electively copying of one or more portions of management data to the non-volatile memory) [Par. 0047; Par. 0015].
With respect to claim 5, MYLAVARAPU teaches memory sub-system, wherein the one or more L2P address mapping tables stored in the ultra-high endurance storage class memory device are not subject to a flush operation (management operation performed on block in non-volatile memory device that does not have an erase-before rewrite requirement) [Par. 043].
With respect to claim 6, MYLAVARAPU teaches memory sub-system, the operations further comprising determining whether an amount of time since a last activity associated with a host system satisfies a threshold condition (initiated media management data comprising management data indicating process such as refresh operation as part of garbage collection operation or refresh operation) [Par. 0033; Par. 0011; Par. 0037].
With respect to claim 7, MYLAVARAPU teaches memory sub-system, the operations further comprising responsive to determining that the amount of time since the last activity associated with the host system satisfies the threshold condition, initiating a flush operation to program at least a portion of the second subset of journals and logs to the primary memory (initiated media management data comprising management data re-writing previously written data (refresh operations) as part of garbage collection management operations) [Par. 0011-0012; Par. 0044].
Claims 8-14, being related to a method having substantially the same technical feature as claims 1-7, methods for copying a portion of management data for a block of a memory device based on activity of the memory device [Fig. 3-5, Fig. 6A and 6B], are rejected based on the same reasoning as in claims 1-7.
Claims 15-20 related to a non-transitory computer-readable storage medium substantially the same technical feature as claims 1-5 and 7, respectively. MYLAVARAPU teaches the data storage device to include a machine-readable storage medium (also known as a computer-readable medium) on which is stored one or more sets of instructions or software embodying any one or more of the methodologies or functions to perform a process [Par. 0062-0063; Par. 0068] described in claims 1-7 and method 8-14. The rejection of claims 1-5 and 7 is applied to claims 15-20 based on the same reasoning.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220188223 A1 (SCHUH et al) teaching processing device modify, in response to the refresh operation, a sequence to replace the one of a plurality of blocks of the sequence with the another one of the plurality of blocks.
US 20220050784 A1 (Das Purkayastha ) teaching method of logical to physical mapping for a data-storage device comprising a non-volatile memory device, the method comprising: maintaining a first type of information representing at least a part of a logical-to-physical address translation map.
A. A. McEwan and I. Mir, "An Embedded FTL for SSD RAID," 2015 Euromicro Conference on Digital System Design, Madeira, Portugal, 2015, pp. 575-582.
Z. Xu, R. Li and C. -Z. Xu, "CAST: A page-level FTL with compact address mapping and parallel data blocks," 2012 IEEE 31st International Performance Computing and Communications Conference (IPCCC), Austin, TX, USA, 2012, pp. 142-151.
Z. Qin, Y. Wang, D. Liu and Z. Shao, "Demand-based block-level address mapping in large-scale NAND flash storage systems," 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Scottsdale, AZ, USA, 2010, pp. 173-182.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET.
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/PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138
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