Prosecution Insights
Last updated: August 17, 2026
Application No. 18/977,168

FAULT DETECTOR AND METHOD FOR DETECTING FAULTS IN COMPONENTS IN A VEHICLE

Non-Final OA §102§103§112
Filed
Dec 11, 2024
Priority
Dec 14, 2023 — EU 23216624.9
Examiner
SANGHERA, JAS A
Art Unit
Tech Center
Assignee
Volvo Group
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
1098 granted / 1161 resolved
+34.6% vs TC avg
Minimal +5% lift
Without
With
+4.9%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
31 currently pending
Career history
1173
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
37.3%
-2.7% vs TC avg
§102
25.9%
-14.1% vs TC avg
§112
28.0%
-12.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1161 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice to Applicant 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 2. Claims 1-15 are pending. Priority 3. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Specification 4. The specification is objected to due to the following informality. On page 13, it appears that the two sentences of paragraph 72 should be combined to form one sentence. Claim Rejections - 35 USC § 112 5. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 6. Claims 1-15 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Per claim 1, the limitation “the HVIL” in line 4 lacks sufficient antecedent basis. Appropriate correction is required. Claims 2-8 are consequently rejected due to their dependence on claim 1. Per claim 9, the limitation “the HVIL” in line 3 lacks sufficient antecedent basis. Appropriate correction is required. Claims 10-15 are consequently rejected due to their dependence on claim 9. Claim Rejections - 35 USC § 102 7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 8. Claims 1-3, 6, 9-11, and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ueda et al. (US 2010/0264878 – hereinafter “Ueda”). Per claim 1, Ueda teaches a method performed by a fault detector (Figs. 1 and 4; integrated circuit (IC); ¶19) for detecting faults in components in a vehicle (¶16), wherein the fault detector is connected in parallel to at least one component of at least two serially connected components (An integrated circuit (IC) is connected in parallel to cells BC of a cell group GB1. The cells BC of the cell group Gb1 are connected in series (¶28)), wherein the HVIL (Fig. 1; power module 226; ¶23) is connected to a first component amongst the at least two serially connected components, wherein the at least two serially connected components are divided into at least two sections, wherein each section comprises at least one component (A power module 226 is electrically connected to a first cell of the plurality of cells BC of the cell group GB1. A first section may comprise the first cell and a second section may comprise a second cell that is adjacent to the first cell (Fig. 4; ¶28)), the method comprising: obtaining a first voltage level at an input point into each section; obtaining a second voltage level at an output point from each section; comparing the first voltage level with the second voltage level for each section and such that the voltage level over each section is determined; and based on a result of the comparison, determining whether or not there is an indication of a fault in each section (Terminals V1 to V4 and a GND terminal of the IC are connected to cells BC1 to BC4 of the cell group GB1. In an over-charge diagnosis, a voltage of the cell BC1, which is measured when an input circuit 116 selects terminals V1 and V2, is compared to an over-charge decision-making reference value OC to determine if an abnormality flag and an over-charge flag should be set in a flag storage circuit 284. This process is repeated with cells BC2 to BC4 (Fig. 4; ¶29, 44, 46, and 48)). Per claim 2, Ueda teaches the method of claim 1, comprising: determining that there is an indication of a fault in the section when the result of the comparing indicates a difference between the first voltage level and the second voltage level and/or indicates that the difference has reached or exceeded a voltage threshold (When the voltage of a cell exceeds the over-charge decision-making reference value OC, an abnormality flag is set (¶46)). Per claim 3, Ueda teaches the method of claim 1, comprising: determining that there is no indication of fault in the section when the result of the comparing does not indicate a difference between the first voltage level and the second voltage level and/or that the difference has not reached or exceeded a voltage threshold (When the voltage of a cell does not exceed the over-charge decision-making reference value OC, an abnormality flag is not set (¶46)). Per claim 6, Ueda teaches the method of claim 1 comprising: storing the first voltage level and/or the second voltage level and/or information indicating the result of the comparison (Cell voltages are stored in a current value storage circuit 274 (Fig. 4; ¶46)). Per claim 9, Ueda teaches a fault detector (Figs. 1 and 4; integrated circuit (IC); ¶19) for detecting faults in components in a vehicle (¶16), wherein the fault detector is arranged to be connected in parallel to at least one component of at least two serially connected components (An integrated circuit (IC) is connected in parallel to cells BC of a cell group GB1. The cells BC of the cell group Gb1 are connected in series (¶28)), wherein the HVIL (Fig. 1; power module 226; ¶23) is arranged to be connected to a first component amongst the at least two serially connected components, wherein the at least two serially connected components are divided into at least two sections, wherein each section comprises at least one component (A power module 226 is electrically connected to a first cell of the plurality of cells BC of the cell group GB1. A first section may comprise the first cell and a second section may comprise a second cell that is adjacent to the first cell (Fig. 4; ¶28)), the fault detector being arranged to: obtain a first voltage level at an input point into each section; obtain a second voltage level at an output point from each section; compare the first voltage level with the second voltage level for each section and such that the voltage level over each section is determined; and to based on a result of the comparison, determine whether or not there is an indication of a fault in each section (Terminals V1 to V4 and a GND terminal of the IC are connected to cells BC1 to BC4 of the cell group GB1. In an over-charge diagnosis, a voltage of the cell BC1, which is measured when an input circuit 116 selects terminals V1 and V2, is compared to an over-charge decision-making reference value OC to determine if an abnormality flag and an over-charge flag should be set in a flag storage circuit 284. This process is repeated with cells BC2 to BC4 (Fig. 4; ¶29, 44, 46, and 48)). Per claim 10, Ueda teaches the fault detector of claim 9, arranged to: determine that there is an indication of a fault in the section when the result of the comparing indicates a difference between the first voltage level and the second voltage level and/or indicates that the difference has reached or exceeded a voltage threshold (When the voltage of a cell exceeds the over-charge decision-making reference value OC, an abnormality flag is set (¶46)). Per claim 11, Ueda teaches the fault detector of claim 9, arranged to: determine that there is no indication of fault in the section when the result of the comparing does not indicate a difference between the first voltage level and the second voltage level and/or that the difference has not reached or exceeded a voltage threshold (When the voltage of a cell does not exceed the over-charge decision-making reference value OC, an abnormality flag is not set (¶46)). Per claim 14, Ueda teaches the fault detection system (Fig. 1; ¶16) for detecting faults in components in a vehicle, the fault detection system comprises a fault detector according to claim 9 and at least two serially connected components. Per claim 15, Ueda teaches a vehicle (Fig. 1; ¶16) comprising the fault detection system according to claim 14. Claim Rejections - 35 USC § 103 9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 10. Claims 4 and 12 are rejected under 35 U.S.C. 103 as being obvious over Ueda in view of Inoue (US 2012/0098547). Per claim 4, Ueda does not explicitly teach the method of claim 1, comprising: when there is an indication of the fault, analyzing the first voltage level and the second voltage level to determine a type and/or a root of the fault. In contrast, Inoue teaches a battery monitoring system comprising a battery cell group 12 including four cells C1 to C4 that is connected to a semiconductor circuit 14 through wires V0 to V4. A type of fault, such as a disconnection or short circuiting, is determined based on the voltages measured by the wires V0 to V4 (Figs. 1 and 4-5; ¶29-30 and 42-50). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ueda such that it comprises, when there is an indication of the fault, analyzing the first voltage level and the second voltage level to determine a type and/or a root of the fault. One of ordinary skill would make such a modification because the voltage value of a cell can be specific to a type of fault (Inoue; Figs. 4-5; ¶42-50). Per claim 12, Ueda does not explicitly teach the fault detector of claim 9, arranged to: when there is an indication of the fault, analyze the first voltage level and the second voltage level to determine a type and/or a root of the fault. In contrast, Inoue teaches a battery monitoring system comprising a battery cell group 12 including four cells C1 to C4 that is connected to a semiconductor circuit 14 through wires V0 to V4. A type of fault, such as a disconnection or short circuiting, is determined based on the voltages measured by the wires V0 to V4 (Figs. 1 and 4-5; ¶29-30 and 42-50). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the detector of Ueda such that it comprises, when there is an indication of the fault, analyzing the first voltage level and the second voltage level to determine a type and/or a root of the fault. One of ordinary skill would make such a modification because the voltage value of a cell can be specific to a type of fault (Inoue; Figs. 4-5; ¶42-50). 11. Claims 5 and 13 are rejected under 35 U.S.C. 103 as being obvious over Ueda in view of Robins et al. (US 2014/0009113 – hereinafter “Robins”). Per claim 5, Ueda does not explicitly teach the method of claim 1, wherein the first voltage level and the second voltage level are obtained continuously. In contrast, Robins teaches a battery system comprising a battery module 304 that is configured to continuously monitor the voltages at cells of a battery 106 to dynamically adjust the amount of energy being added to each cell (¶55). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ueda such the first voltage level and the second voltage level are obtained continuously. One of ordinary skill would make such a modification for the purpose of protecting against an over charge condition (Robins; ¶55). Per claim 13, Ueda does not explicitly teach the fault detector of claim 9, wherein the first voltage level and the second voltage level are obtained continuously. In contrast, Robins teaches a battery system comprising a battery module 304 that is configured to continuously monitor the voltages at cells of a battery 106 to dynamically adjust the amount of energy being added to each cell (¶55). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the detector of Ueda such the first voltage level and the second voltage level are obtained continuously. One of ordinary skill would make such a modification for the purpose of protecting against an over charge condition (Robins; ¶55). 12. Claim 7 is rejected under 35 U.S.C. 103 as being obvious over Ueda in view of Bernstein et al. (US 2013/0127611 – hereinafter “Bernstein”). Per claim 7, Ueda does not explicitly teach the method of claim 6, wherein the storing of the first voltage level and/or second voltage level and/or information indicating the result of the comparison is triggered by that the difference between the first voltage level and the second voltage level has reached or exceeded the voltage threshold. In contrast, Bernstein teaches a battery system wherein, when a battery monitor 12 determines that a measured voltage is not an acceptable voltage, the battery monitor 12 may store the measured voltage in an abnormal event log (¶94). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ueda such that the storing of the first voltage level and/or second voltage level and/or information indicating the result of the comparison is triggered by that the difference between the first voltage level and the second voltage level has reached or exceeded the voltage threshold. One of ordinary skill would make such a modification for the purpose of maintaining an abnormal event log (Bernstein; ¶94). 13. Claim 8 is rejected under 35 U.S.C. 103 as being obvious over Ueda in view of Cheon et al. (US 2019/0195942 – hereinafter “Cheon”). Per claim 8, Ueda does not explicitly teach the method of claim 1, wherein the first voltage level and the second voltage level are obtained at a sampling rate below 10 milliseconds. In contrast, Cheon teaches a battery system comprising a voltage measuring part 210 connected to secondary batteries 11-14 wherein a voltage at both ends of the first secondary battery 11 is measured at a first time and at a second time 1 ms after the first time (Fig. 1; ¶36 and 46). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ueda such that the first voltage level and the second voltage level are obtained at a sampling rate below 10 milliseconds. One of ordinary skill would make such a modification for the purpose of determining whether a current is flowing through a battery based on a measured voltage deviation (Cheon; ¶46 and 54). Conclusion 14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAS A. SANGHERA whose telephone number is (571)272-4787. The examiner can normally be reached M-Th, alt. Fri, 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WALTER LINDSAY can be reached at (571) 272-1674. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAS A SANGHERA/Primary Examiner, Art Unit 2852
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Prosecution Timeline

Dec 11, 2024
Application Filed
Jul 24, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
99%
With Interview (+4.9%)
1y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1161 resolved cases by this examiner. Grant probability derived from career allowance rate.

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