Prosecution Insights
Last updated: October 01, 2026
Application No. 18/977,345

POWER CONVERSION DEVICE, ENERGY STORAGE SYSTEM, AND CONTROL METHOD THEREFOR

Non-Final OA §102§103
Filed
Dec 11, 2024
Priority
Dec 14, 2023 — CN 202311719943.5
Examiner
SOILEAU, JONATHAN WALTER
Art Unit
Tech Center
Assignee
Huawei Technologies Co., Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
22 granted / 24 resolved
+31.7% vs TC avg
Moderate +10% lift
Without
With
+10.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
8 currently pending
Career history
32
Total Applications
across all art units

Statute-Specific Performance

§103
50.0%
+10.0% vs TC avg
§102
37.0%
-3.0% vs TC avg
§112
13.0%
-27.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 24 resolved cases

Office Action

§102 §103
Detailed Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 1/30/2025 and 6/11/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2, 10-11 and 19-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Gajanayake (U.S. Publication No 2019/0312527 A1). Regarding claims 1 and 10, Gajanayake teaches a power conversion device, comprising: a direct current (DC)/DC conversion circuit (e.g. 110/112/114)(Fig. 1), wherein a first end (e.g. top of 112 and bottom of 114)(Fig. 1) of the DC/DC conversion circuit is configured to connect to an energy storage unit (e.g. 111)(Fig. 1); and a DC/alternating current (AC) conversion circuit (e.g. 150)(Fig. 1), wherein a first end (e.g. Top of 151a and bottom of 151b)(Fig. 1) of the DC/AC conversion circuit is connected to a second end (e.g. top of 120 and top of 121)(Fig. 1) of the DC/DC conversion circuit, the first end of the DC/AC conversion circuit comprises: a positive bus (e.g. 115)(Fig. 1), a negative bus (e.g. 116)(Fig. 1), and a neutral line (e.g. 124)(Fig. 1), and a second end of the DC/AC conversion circuit is configured to connect to an alternating current power grid and/or a load (abstract, “The DC-AC stage has a plurality of DC-AC stage switches connected between the positive rail and the negative rail and operable to produce the one or more phases of AC power at the output of the DC-AC stage”), an input voltage of the DC/DC conversion circuit is a voltage between the positive bus and a positive end of the energy storage unit (Para [0025], “The received DC power may have a voltage of 270V, and the DC-DC stage may be operable to provide a 160V voltage to the positive rail and a −160V voltage to the negative rail, and the DC-AC stage may be operable to convert the converted DC power to 115V AC”)(see Fig. 1), a voltage between the positive end of the energy storage unit and the neutral line, a voltage between the neutral line and a negative end of the energy storage unit, or a voltage between the negative end of the energy storage unit and the negative bus, and an output voltage of the DC/DC conversion circuit is half of a direct current bus voltage (Para [0050], “The switches are operated so as to provide a voltage 122 on the positive rail and a voltage 123 to be provided on the negative rail. These voltages are a potential difference between the respective rail and a zero rail 124, which is at zero potential. In one example, the voltage 122 on the positive rail is 160 V and the voltage 123 on the negative rail is −160 V. Capacitor 120 is connected between the positive rail 115 and the zero rail 124, and capacitor 121 is connected between the negative rail 116 and the zero rail 124”). Regarding claims 2 and 11, Gajanayake teaches wherein the DC/DC conversion circuit comprises a first DC/DC conversion circuit (e.g. 110/112/114)(Fig. 1), a negative end (e.g. 114)(Fig. 1) of a first end of the first DC/DC conversion circuit is configured to connect to the positive end (e.g. + 111)(Fig. 1) of the energy storage unit (Para [0054], “Both switches 112 and 114 are closed, and therefore diodes 117 and 118 are in a non-conducting state”), a positive end (e.g. 112)(Fig. 1) of the first end of the first DC/DC conversion circuit and a positive end (e.g. top of 120)(Fig. 1) of a second end of the first DC/DC conversion circuit are connected to the positive bus (e.g. 115)(Fig. 1), and a negative end (e.g. top of 121)(Fig. 1) of the second end of the first DC/DC conversion circuit is connected to the neutral line (e.g. bottom of 121 goes to 124)(Fig. 1). Regarding claims 19 and 20, Gajanayake teaches wherein the DC/DC conversion circuit comprises a first DC/DC conversion circuit (e.g. 110)(Fig. 1), a positive end (e.g. top of 112)(Fig. 1) of a first end of the first DC/DC conversion circuit is configured to connect to the positive end of the energy storage unit (e.g. + 111)(Fig. 1), a positive end (e.g. top of 120)(Fig. 1) of a second end of the first DC/DC conversion circuit is connected to the positive bus (e.g. 115)(Fig. 1) of the DC/AC conversion circuit, and a negative end (e.g. bottom of 114)(Fig. 1) of the first end of the first DC/DC conversion circuit and a negative end (e.g. top of 121)(Fig. 1) of the second end of the first DC/DC conversion circuit are connected to the neutral line (e.g. 124)(Fig. 1). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3-4 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Gajanayake (U.S. Publication No 2019/0312527 A1) in view of Gurunathan et. al. (U.S. Publication No 2011/0278935 A1). Regarding claims 3 and 12, although Gajanayake teaches the limitations in claims 1 and 10, Gajanayake does not teach a plurality of DC/DC conversion circuits that comprises: at least one first DC/DC conversion circuit; and at least one second DC/DC conversion circuit. However, Gurunathan et. al. teaches a plurality of DC/DC conversion circuits (e.g. 234/236/218)(Fig. 2) that comprises: at least one first DC/DC conversion circuit (e.g. 234)(Fig. 2); and at least one second DC/DC conversion circuit (e.g. 236)(Fig. 2). Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “power conversion device” teachings of Gajanayake such that it comprises “a plurality of DC/DC conversion circuits that comprises: at least one first DC/DC conversion circuit; and at least one second DC/DC conversion circuit” as taught by Gurunathan et. al. The reason for doing so would be to provide lower power from multiple DC converters instead of higher power from one converter, thus reducing component damages. Regarding claims 4 and 13, Gurunathan et. al. teaches wherein the at least one first DC/DC conversion circuit and the at least one second DC/DC conversion circuit are configured to: jointly control a voltage from the positive bus to the negative bus to meet a target input voltage of the DC/AC conversion circuit, and reduce a difference between a voltage from the positive bus to the neutral line and a voltage from the neutral line to the negative bus. (Para [0030], “The DC/DC converters 234, 236 or 238 are generally boost converters and serve to bring the +ve output bus 264 to a voltage level with respect to neutral line 232 appropriate for the power system application. The negative terminals of fuel cell segments 204, 208 and 212 are also connected to output busses 220, 222 and 224 respectively, leading to DC/DC converters 244, 242 and 240 respectively. These DC/DC converters serve the same function as DC/DC converters 234, 236 and 238, albeit with an opposite polarity, bringing the voltage on -ve bus 266 to a suitably negative level with respect to neutral line 232”). Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Gajanayake (U.S. Publication No 2019/0312527 A1) in view of Suzuki et. al. (U.S. Publication No 2026/0196949 A1). Regarding claims 9 and 18, although Gajanayake teaches the limitations in claims 2 and 11, Gajanayake does not teach wherein the DC/AC conversion circuit is: a two-level conversion circuit, a three-level conversion circuit, or a multi-level conversion circuit. However, Suzuki et. al. teaches wherein the DC/AC conversion circuit is: a two-level conversion circuit, a three-level conversion circuit (e.g. 30)(Fig. 1), or a multi-level conversion circuit. Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “power conversion device” teachings of Gajanayake such that it comprises “wherein the DC/AC conversion circuit is: a two-level conversion circuit, a three-level conversion circuit, or a multi-level conversion circuit” as taught by Suzuki et. al. The reason for doing so would be because it allows for a specific design choice, which can provide a reduction in component variance, thus increasing operational efficiencies. Allowable Subject Matter Claims 5-8 and 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claims 5 and 14, none of the prior art, taken singly or in combination, teach “a first switch connected in parallel between the positive end of the first end of the first DC/DC conversion circuit and the positive end of the second end of the first DC/DC conversion circuit, and when a voltage between the positive end and the negative end of the energy storage unit is greater than or equal to a first voltage threshold, the first switch is turned on, and the DC/DC conversion circuit does not operate”. Regarding claims 6 and 15, none of the prior art, taken singly or in combination, teach “a second switch connected in series between the positive end of the energy storage unit and the first end of the first DC/DC conversion circuit, and when the voltage between the positive end and the negative end of the energy storage unit is less than or equal to a second voltage threshold, the second switch is turned off”. Regarding claims 7 and 16, none of the prior art, taken singly or in combination, teach “a soft-start circuit that comprises a first branch and a second branch, wherein the first branch is connected in series between the positive end of the energy storage unit and the first end of the first DC/DC conversion circuit, the second branch is connected in parallel to two ends of the first branch, the second branch is connected in series to a first resistor, when the energy storage system is started up and the energy storage unit starts to provide electric energy, the first branch is disconnected, and the second branch is connected, and, after the energy storage unit provides the electric energy, when a voltage between the two ends of the first branch is less than a third voltage threshold, the first branch is connected”. Regarding claims 8 and 17, none of the prior art, taken singly or in combination, teach “a balanced circuit configured to: operate when an absolute value of a voltage difference between the positive bus and the negative bus is greater than or equal to a fourth voltage threshold, to reduce the difference between the voltage from the positive bus to the neutral line and the voltage from the neutral line to the negative bus, and not operate when the absolute value of the voltage difference between the positive bus and the negative bus is less than the fourth voltage threshold”. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN W SOILEAU whose telephone number is (571)272-6650. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hammond L Crystal can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JONATHAN WALTER SOILEAU/Examiner, Art Unit 2838 /CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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Prosecution Timeline

Dec 11, 2024
Application Filed
Aug 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+10.5%)
2y 4m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 24 resolved cases by this examiner. Grant probability derived from career allowance rate.

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