DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 21 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2, 4 – 9, 12, 13, and 20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 4, 6, and 18 of U.S. Patent No. 10,789,186. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the patent require all the limitations of the claims of the instant application (see chart below).
Instant Application
10,789,186
1
1
2
1
4
6
5
6
6
2
7
2
8
3
9
4
12
18
13
18
20
18
Allowable Subject Matter
Claims 1 – 21 would be allowable if rewritten, amended, or a proper terminal disclaimer is filed to overcome the non-statutory double patenting rejection(s) set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 1 – 11 would be allowable if rewritten, amended, or a proper terminal disclaimer is filed to overcome the non-statutory double patenting rejection(s) set forth in this Office action because the prior art of record fails to teach or suggest alone or in combination providing a timing command to a memory, the timing command configured to set a delay for when an input buffer of the memory is disabled following an access command associated with the timing command; providing the access command to the memory; and providing a data clock signal to the input buffer of the memory, as required by independent claim 1, in combination with the other claimed limitations (emphasis added). US Patent No. 6,337,833 teaches supplying a clock for a period defined by a CAS latency and burst length (Col 5 Lines 1 – 22), but does not teach the timing command configured to set a delay for when an input buffer of a memory is disabled following an access command associated with the timing command, providing the access command to the memory, and providing a data clock to the input buffer of the memory, as required by independent claim 1. US Patent Application Publication No. 2004/0215996 teaches delaying an output enable signal by a delay time (Paragraphs [0107] – [0111]), but does not teach the timing command configured to set a delay for when an input buffer of a memory is disabled following an access command associated with the timing command, providing the access command to the memory, and providing a data clock to the input buffer of the memory, as required by independent claim 1.
Claims 2 – 11 would also be allowable because of their dependence, either directly or indirectly, upon allowable independent claim 1.
Claims 12 – 21 would be allowable if rewritten, amended, or a proper terminal disclaimer is filed to overcome the non-statutory double patenting rejection(s) set forth in this Office action because the prior art of record fails to teach or suggest alone or in combination providing a timing command to a memory, the timing command configured to set a delay for when an input buffer of the memory is disabled following an access command associated with the timing command; providing the access command to the memory; and providing a data clock signal to the input buffer of the memory, as required by independent claim 12, in combination with the other claimed limitations (emphasis added). US Patent No. 6,337,833 teaches supplying a clock for a period defined by a CAS latency and burst length (Col 5 Lines 1 – 22), but does not teach the timing command configured to set a delay for when an input buffer of a memory is disabled following an access command associated with the timing command, providing the access command to the memory, and providing a data clock to the input buffer of the memory, as required by independent claim 12. US Patent Application Publication No. 2004/0215996 teaches delaying an output enable signal by a delay time (Paragraphs [0107] – [0111]), but does not teach the timing command configured to set a delay for when an input buffer of a memory is disabled following an access command associated with the timing command, providing the access command to the memory, and providing a data clock to the input buffer of the memory, as required by independent claim 12.
Claims 13 – 21 would also be allowable because of their dependence, either directly or indirectly, upon allowable independent claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm.
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/RICHARD B FRANKLIN/ Examiner, Art Unit 2181