DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 12/11/2024 and 10/23/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-14 and 16-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Gopal et al. (US 2013/0326201) (an IDS reference cited by the Applicant).
As per claims 1 and 11, Gopal teaches a computer system (Gopal: par. [0001]; fig. 4)/a method implemented by a computer system (Gopal: claim 1), comprising:
a data memory configured to store a byte array (Gopal: fig. 8, item 809);
a program memory configured to store a computer program (Gopal: pars. [0029], [0057]);
a digital signal processor configured to execute the computer program to access each byte of the byte array (Gopal: fig. 8, item 850; par. [0058]; claim 11); and
a circuit that accesses a bit of a byte of the byte array (Gopal: par. [0066]: “On a byte-oriented processor, each time bits are consumed”) by being configured to: obtain a bit position pointer that points to the bit to be accessed in the byte array (Gopal: fig. 8, item 803; par. [0067]: “where PR is a pointer register 803 containing a bit address 804”); and obtain a byte that includes the bit to be accessed (Gopal: par. [0069]: “at the start of processing, the byte pointer address P and length in bytes L of the input bit stream 815 is used by the bit pointer update logic 806 for generating the corresponding "bit" pointers”).
As per claims 2 and 12, Gopal teaches wherein the circuit is further configured to calculate a byte shift value according to a value of the bit position pointer (Gopal: par. [0080]).
As per claims 3 and 13, Gopal teaches wherein the circuit includes: a first logical conjunction gate configured to perform a first logical conjunction on the value of the bit position pointer and a hexadecimal value 0x7 to obtain an index value; and a comparison circuit configured to: compare the index value and 0; set the byte shift value to -1 when the index value is equal to 0; and set the byte shift value to 0 when the index value is not equal to 0 (Gopal: pars. [0079] –[0083]).
As per claims 4 and 14, Gopal teaches wherein the circuit is further configured to determine a value of the bit to be read from the bit position pointer and the byte (Gopal: par. [0080]).
As per claim 16, Gopal teaches wherein determining the value of the bit to be read is based on the bit position pointer and a byte pointer and includes: calculating a byte shift value; updating the byte pointer based on the byte shift value; and determining the value of the bit to be read based on the updated byte pointer (Gopal: pars. [0079] – [0083]).
As per claims, 7 and 17, Gopal teaches wherein the circuit is configured to write the value of a bit instead of a bit pointed to by the bit position pointer in the byte on which to write (Gopal: pars. [0072], [0085]).
As per claims 9 and 19, Gopal teaches wherein the computer program includes instructions that, when executed by the digital signal processor, cause the digital signal processor to perform at least one call of a write bit function to write a bit in the byte array, wherein each call of the write bit function has the bit position pointer and a byte pointer as inputs, wherein the instructions cause the digital signal processor to: calculate a byte shift value; update the byte pointer based on the byte shift value; and write the value of the bit based on the updated byte pointer (Gopal: pars. [0085] – [0091]).
As per claims 10 and 20, Gopal teaches wherein the computer program includes instructions that, when executed by the digital signal processor, cause the digital signal processor to initiate the bit position pointer to point towards the position of the last bit of the byte array, and to decrement the bit position pointer at each read or write access (Gopal: pars. [0069], [0082]).
Allowable Subject Matter
Claims 5, 6 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
As per claims 5 and 15, prior arts of record fail to teach or suggest wherein the circuit comprises: an adder circuit configured to increase the value of the bit position pointer by 1; a second logical conjunction gate configured to perform a second logical conjunction on the increased value of the bit position pointer and a hexadecimal value equal to 0x7; a subtractor circuit configured to calculate a shift value by subtracting a value equal to 7 from the output of the second logical conjunction; a shift circuit configured to shift to the right the value of the byte by a number of bits corresponding to the shift value; and a third logical conjunction gate configured to perform a third logical conjunction on a value equal to 1 and the shifted value of the byte to obtain the value of the bit to be read.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li et al. (US 5,835,793) teaches a data processing device providing get bit-field instruction to extract bit from the data stream.
Morad et al. (US 2008/0240093) teaches an apparatus providing a get-bits and put-bits instructions to obtain bits from the bit stream.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAUSHIKKUMAR M PATEL whose telephone number is (571)272-5536. The examiner can normally be reached Mon-Fri: 9:00 AM - 5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim T Vo can be reached at 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Kaushikkumar M. Patel
Primary Examiner
Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138