DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to communication from applicant received on June 10, 2026.
Response to Amendment
Applicant's submission filed on June 10, 2026 has been entered. Claims 1-20 are pending in the current application. Claims 1-20 are rejected herein.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (Hereinafter Lee, U.S. Publication No. 2023/0359379).
Regarding claim 1, Lee teaches:
A method, comprising:
connecting a compute express link fabric to a plurality of memory devices and a host processor (See [0161] “the CXL switch SW_CXL may be connected with an external network or Fabric and may be configured to communicate with an external server through the external network or Fabric.” See [0034] “Compute eXpress Link (CXL) storage 110, and a CXL memory 120.” See Figures 2-4, 6-14 and 17, which teach a compute express link fabric to be connected to a host and a plurality of memory devices.);
allocating, by the compute express link fabric, memory resources from the memory devices (See Figure 4, Allocate Memory & Write Map data. See [0088] “For example, in operation PUP-S41, the CXL storage 110 may output a memory allocation request REQ_mem_alc through the CXL storage interface circuit 111a. The memory allocation request REQ_mem_alc may be transferred to the CXL switch SW_CXL.”) to implement a logical memory device attached to the host processor (See [0090] “In an example embodiment, the memory allocation response REP_mem_alc may include information about a device identifier of the CXL memory 120 and a memory address (e.g., a logical address range or a virtual address range) of an area of the CXL memory 120, which is allocated for a dedicated area of the CXL memory 120.” See [0068] “In an example embodiment, the memory address that is an address for managing a storage area of the CXL memory 120 may be a logical address or a virtual address that is designated and managed by the host 101.”); and
maintaining, in the compute express link fabric, a mapping between memory addresses in the logical memory device and the memory resources to route memory access requests having the memory addresses to access the memory resources in the memory devices (See [0053] “The CXL storage 110 may include the CXL storage controller 111 and the nonvolatile memory NVM. The CXL storage controller 111 may include a CXL storage interface circuit 111a, a processor 111b, a RAM 111c, a flash translation layer (FTL) 111d”. See [0056] “the FTL 111d may perform address translation between a logical block address managed by the host 101 and a physical block address used in the nonvolatile memory NVM, based on map data (or a mapping table).” See [0068] “the memory manager 121c may be configured to translate a memory address (e.g., a logical address or a virtual address) from the host 101 or the CXL storage 110 into a physical address for the buffer memory BFM”).
Regarding claim 9, Lee teaches:
A system, comprising:
a compute express link fabric having a controller (See the compute express link (CXL) storage controller 111 and CXL memory controller 121 depicted in Figure 2 and Figure 3.);
a plurality of memory devices connected to the compute express link fabric; and
a plurality of host processors connected to the compute express link fabric (See [0161] “the CXL switch SW_CXL may be connected with an external network or Fabric and may be configured to communicate with an external server through the external network or Fabric.” See [0034] “Compute eXpress Link (CXL) storage 110, and a CXL memory 120.” See [0158] “In an example embodiment, each of the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140 may correspond to the hosts described with reference to FIGS. 1 to 14 and may be directly connected with individual memory devices.” See Figures 2-4, 6-14 and 17, which teach a compute express link fabric to be connected to a host and a plurality of memory devices. See Figure 15 and [0158], which teaches multiple hosts to be connected to the compute express link (CXL) fabric.);
wherein the controller is configured to attach, at a boot time of the system (See [0078] “FIG. 4 is a flowchart illustrating an initialization operation or a power-up operation of a computing system of FIG. 3, according to an example embodiment. Referring to FIGS. 3 and 4, in operation PUP-S10, the computing system 100 may be powered up. When the computing system 100 is powered up, the host 101 may send information about power-up or initialization start to the CXL storage 110, the CXL switch SW_CXL, and the CXL memory 120. In response to the information about power-up or initialization start, each of the CXL storage 110, the CXL switch SW_CXL, and the CXL memory 120 may perform an individual initialization operation.”), a logical memory device to a host processor among the plurality of host processors (See [0068] “In an example embodiment, the memory address that is an address for managing a storage area of the CXL memory 120 may be a logical address or a virtual address that is designated and managed by the host 101.”); and
wherein the controller is further configured to allocate memory resources from the memory devices to implement the logical memory device using a mapping between memory addresses in the logical memory device and the memory resources to route memory access requests having the memory addresses to access the memory resources in the memory devices (See rejection of claim 1.).
Claim 17 is rejected for the same reasons as claim 9.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-8, 10-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Choi et al. (Hereinafter Choi, U.S. Publication No. 2023/0289074).
Regarding claim 2, Choi teaches:
The method of claim 1, further comprising:
receiving, in the compute express link fabric, a request from the host processor to change a capacity size of the logical memory device attached to the host processor (See Figure 2, step 242. See the compute express link CXL depicted in Figure 2. See [0054] “In step 242, the host 220 initiates an “add capacity” function by an orchestrator/FM configuration.”. See [0020] “a communication method between a host agent and a target agent connected by a switching fabric (SF) disposed between the host agent and the target agent, includes initiating, by the host agent, an add capacity function, transmitting, by a host-managed device memory (HDM) decoder disposed in the SF, an updated configuration to the target agent, sending, by the target agent, the updated configuration to the host agent, performing a dynamic memory capacity expansion process between the host agent and the target agent.” See claim 1 of Choi “a host; a processor; a memory pooling device electrically connected to the processor; and a compute express link (CXL) dynamic memory capacity expansion device (DMCED), wherein the CXL DMCED is directly electrically connected to the memory pooling device.” See claim 5 of Choi “The device of claim 2, further comprising: a switching fabric (SF) disposed between the host and the memory pooling device and CXL DMCED.” See Figures 1-3 in which a host is connected to system components via a compute express link (CXL) fabric. The CXL DMCED may correspond to the claimed logical device.); and
adjusting, by the compute express link fabric in response to the request, the mapping to change the capacity size of the logical memory device without restarting a computing system containing the host processor (See abstract “Disclosed is a device including a host, a processor, a memory pooling device electrically connected to the processor, and a compute express link (CXL) dynamic memory capacity expansion device (DMCED), wherein the CXL DMCED is directly electrically connected to the memory pooling device and at least one of a memory capacity or a storage capacity in the memory pooling device is configured to be increased and decreased while maintaining an active power state of the device.” See [0046] “Each architecture in FIG. 1 enables memory capacity to change while maintaining an active power state of the DMCED 105, without the need for resetting the device/system by a power cycle.” See [0052] “The HDM decoder 212 is used to determine device physical address (DPA) and host physical address (HPA) mappings, i.e., in order for the host 220 to access the memory area in the target 205.” Under broadest reasonable interpretation, adjusting a memory capacity would involve adjusting the associated mappings for the memory, as increasing/decreasing the memory capacity would involve increasing/decreasing the mappings associated with the memory.);
wherein the request is communicated in accordance with a standard for compute express link (CXL) (See Figures 1-7, which depict communications in accordance with a compute express link (CXL).); and the logical memory device is attached to the host processor as a dynamic capacity device (See Figures 1-7 in which a dynamic memory capacity expansion device (DMCED) is attached to the host, and corresponds to the claimed logical memory device.).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the CXL system of Lee with the compute express link (CXL) dynamic memory capacity expansion device (DMCED) methods of Choi to reduce downtime needed for memory capacity reconfigurations, thus improving system performance when performing memory reconfigurations.
Regarding claim 3, Lee teaches:
The method of claim 2, wherein the memory resources are allocated from more than one of the memory devices to implement the logical memory device (See [0090] “In an example embodiment, the memory allocation response REP_mem_alc may include information about a device identifier of the CXL memory 120 and a memory address (e.g., a logical address range or a virtual address range) of an area of the CXL memory 120, which is allocated for a dedicated area of the CXL memory 120.” See [0068] “the memory manager 121c may be configured to translate a memory address (e.g., a logical address or a virtual address) from the host 101 or the CXL storage 110 into a physical address for the buffer memory BFM. In an example embodiment, the memory address that is an address for managing a storage area of the CXL memory 120 may be a logical address or a virtual address that is designated and managed by the host 101”. See Figure 14 in view of [0078] and [0090], which teaches multiple memory devices CXL storage and CXL memory to be used to implement the logical memory device(s).).
Regarding claim 3, Choi teaches:
The method of claim 2, wherein the memory resources are allocated from more than one of the memory devices to implement the logical memory device (See [0059] “In FIG. 4, the host 420 and the DMCED 405 connected thereto are identical to the host and DMCED described above in FIGS. 1-3. In the dynamic memory expansion device 400 including device add/detach 450, a device attach and/or device_detach communication is performed between the host 420 connected to the target DMCED 405. Based on these communications, a device may be added to or detached from the device 450. In the dynamic memory expansion device 400 including add/release capacity 451, a set/get feature 453 and an add_capacity/release_capacity feature 454 are performed between the host 420 and the target DMCED 405, by which memory capacity may be selectively added or released.” The dynamic memory expansion device (DCMED) may comprise more than one memory devices, as it may involve adding memory devices to dynamically increase/expand the memory capacity.).
Regarding claim 4, Lee teaches:
The method of claim 3, further comprising:
receiving, in the compute express link fabric and from the host processor, a capacity query for the logical memory device prior to the request (See Figure 4. See [0081] “in operation PUP-S21, the host 101 may issue a first device information request REQ_id1 for recognizing device information of the CXL storage 110 through the CXL host interface circuit 101a. The first device information request REQ_id1 may be transferred to the CXL switch SW_CXL.” See [0083] “The host 101 may identify the device information of the CXL storage 110 in response to the first device information response REP_id1 received from the CXL switch SW_CXL. In an example embodiment, the first device information response REP_id1 may include information about a device type and a storage capacity of the CXL storage 110” See [0161] “the CXL switch SW_CXL may be connected with an external network or Fabric and may be configured to communicate with an external server through the external network or Fabric.” See [0084] and [0086]. In paragraphs [0081], [0083], [0084] and [0086], and Figure 4, the prior art teaches a host to send requests REQ_id1 and REQ_id2 for storage capacity, which are received by a compute express link (CXL) fabric.);
determining, by the compute express link fabric in response to the capacity query, an amount of memory resources in the memory devices that are currently available for allocation to the logical memory device (See Figure 4, Allocate Memory & Write Map data. See [0019] “For example, the FTL 111d of the CXL storage controller 111 may manage block information about a memory block, which is free, capable of being written, or capable of being allocated, from among memory blocks included in the nonvolatile memory NVM.” See [0202] “When the capacity of the free memory FM in the buffer memory BFM is determined to be greater than a reference capacity for storing the first map data MD1 and the number of CXL storages that the CXL memory 620 currently manages is smaller than the reference number, the CXL memory 620 may authorize the use permission to the first CXL storage 610_1.” See [0090] “The CXL switch SW_CXL may transfer the memory allocation response REP_mem_alc to the CXL storage 110 targeted for the memory allocation response REP_mem_alc. In an example embodiment, the memory allocation response REP_mem_alc may include information about a device identifier of the CXL memory 120 and a memory address (e.g., a logical address range or a virtual address range) of an area of the CXL memory 120, which is allocated for a dedicated area of the CXL memory 120.” See [0091] “The CXL storage 110 may identify the area of the CXL memory 120, which is dedicated for the CXL storage 110, based on the memory allocation response REP_mem_alc.”); and
identifying, to the host processor by the compute express link fabric based on the amount and in response to the capacity query, a maximum available capacity of the logical memory device (See [0082] “In operation PUP-522, the CXL storage 110 may output a first device information response REP_id1 through the CXL storage interface circuit 111a in response to the first device information request REQ_id1 received from the CXL switch SW_CXL. The first device information response REP_id1 may be transferred to the CXL switch SW_CXL. The CXL switch SW_CXL may transfer the first device information response REP_id1 to the host 101 targeted for the first device information response REP_id1.” See [0083] “The host 101 may identify the device information of the CXL storage 110 in response to the first device information response REP_id1 received from the CXL switch SW_CXL. In an example embodiment, the first device information response REP_id1 may include information about a device type and a storage capacity of the CXL storage 110.” See Figure 4 in view of paragraphs [0082], [0083], [0085] and [0086], in which responses REP_id1 and REP_id2 are sent to the host by the compute express link fabric.).
Regarding claim 5, Lee teaches:
The method of claim 4, wherein the request from the host processor identifies a requested capacity size of the logical memory device that is no larger than the maximum available capacity (See [0202] “When the capacity of the free memory FM in the buffer memory BFM is determined to be greater than a reference capacity for storing the first map data MD1 and the number of CXL storages that the CXL memory 620 currently manages is smaller than the reference number, the CXL memory 620 may authorize the use permission to the first CXL storage 610_1.” See Figure 4.).
Regarding claim 6, Lee teaches:
The method of claim 5, wherein the requested capacity size is larger than a capacity size of the logical memory device at a time when the request is received in the compute express link fabric (See [0202] “When the capacity of the free memory FM in the buffer memory BFM is determined to be greater than a reference capacity for storing the first map data MD1 and the number of CXL storages that the CXL memory 620 currently manages is smaller than the reference number, the CXL memory 620 may authorize the use permission to the first CXL storage 610_1.” Se figure 4).
Regarding claim 7, Lee teaches:
The method of claim 6, further comprising:
generating, by the compute express link fabric after completion of the adjusting, a response to the request (See [0095] “In operation PUP-546, the CXL storage 110 may output acknowledge information ACK_md through the CXL storage interface circuit 111a. The CXL switch SW_CXL may transfer the acknowledge information ACK_md to the host 101. In response to the acknowledge information ACK_md, the host 101 may recognize that the CXL storage 110 stores the map data MD in the CXL memory 120.”).
Regarding claim 7, Choi teaches:
The method of claim 6, further comprising:
generating, by the compute express link fabric after completion of the adjusting, a response to the request (See [0020] “sending, by the target agent, the updated configuration to the host agent, performing a dynamic memory capacity expansion process between the host agent and the target agent, and performing a confirmation process between the host agent and the target agent, the confirmation process including an add_complete and/or a release_complete communication.” See [0054] “In step 248, a confirmation process is performed between the host CXL agent 213a and the target CXL agent 213b, including an add_complete and/or a release_complete communication.”).
Regarding claim 8, Lee teaches:
The method of claim 3, wherein the request from the host processor identifies a requested capacity size of the logical memory device (See [0083] “The host 101 may identify the device information of the CXL storage 110 in response to the first device information response REP_id1 received from the CXL switch SW_CXL. In an example embodiment, the first device information response REP_id1 may include information about a device type and a storage capacity of the CXL storage 110.” See [0087] “the host 101 may identify the information about the device types (e.g., a storage type or a memory type) and capacities of the CXL storage 110 and the CXL memory 120 through operation PUP-S21 to operation PUP-S32.”) that is smaller than a capacity size of the logical memory device at a time when the request is received in the compute express link fabric (See [0202] “When the capacity of the free memory FM in the buffer memory BFM is determined to be greater than a reference capacity for storing the first map data MD1 and the number of CXL storages that the CXL memory 620 currently manages is smaller than the reference number, the CXL memory 620 may authorize the use permission to the first CXL storage 610_1.” Se figure 4).
Claim 10 is rejected for the same reasons as claim 2 and claim 3 (See Figure 3 and Figure 4 of Lee, which teaches the CXL switch). Claim 11 is rejected for the same reasons as claim 2. Claim 13 is rejected for the same reasons as claim 5. Claim 14 is rejected for the same reasons as claim 6. Claim 16 is rejected for the same reasons as claim 8. Claim 18 is rejected for the same reasons as claim 10. Claim 12 and claim 19 are rejected for the same reasons as claim 4. Claim 15 and claim 20 are rejected for the same reasons as claim 7.
Response to Arguments
Applicant's arguments filed June 10, 2026 have been fully considered but they are not persuasive. On page 1 of applicant’s arguments, applicant submitted that claim 1 recites “a logical memory device attached to the host processor”, and that Lee does not discuss such a “logical memory device” that is attached to a “host processor”. Examiner respectfully disagrees. Applicant submitted that (Pars. [0068, 0089 and 0090]) merely discuss a “memory allocation request” and a “memory allocation response” in connection with “a logical address or a virtual address”, and that such discussions are seen irrelevant to the “logical memory device” and its implementation as recited in claim 1. Applicant further submitted that the “logical address” in Par. [0068] of Lee is a “virtual address” in the host 101 of Lee and thus irrelevant to a “logical memory device attached to the host processor”. Examiner respectfully disagrees. See [0090] of Lee “the memory allocation response REP_mem_alc may include information about a device identifier of the CXL memory 120 and a memory address (e.g., a logical address range or a virtual address range) of an area of the CXL memory 120, which is allocated for a dedicated area of the CXL memory 120.” See [0068] of Lee “In an example embodiment, the memory address that is an address for managing a storage area of the CXL memory 120 may be a logical address or a virtual address that is designated and managed by the host 101.” Paragraph [0068] and [0090] both indicate that the CKL memory 120 may correspond to logical memory by having a logical address range designated and managed by the host. Furthermore, paragraph [0068] explicitly indicates the logical address range of the CXL memory 120 to be designated and managed by the host 101, which would indicate that it is connected/attached to the host. Since applicant’s arguments are not persuasive, all pending claims in the instant application remain rejected under the cited prior art of record.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL L WESTBROOK whose telephone number is (571)270-5028. The examiner can normally be reached Mon-Fri 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL L WESTBROOK/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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