DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 31 October 2025 have been fully considered but they are not persuasive.
First, the applicant states, on page 10 of the response, that Han et al. was used in the rejection of dependent claim 3 “yet offers no rationale to substantiate this assertion.” However, dependent claim 3 previously recited three limitations with “or” statements between, meaning that only one of the limitations was required. Applicant has now chosen one of the limitations not chosen in the previous Office Action to add into claim 1. Han et al. was never used to reject the “width-to-length ratio” limitations.
Further, on page 11 of the response, the applicant argues that Lai et al. teaches of transistors in a shift register, not in the PAM driving circuit, and thus Han and Lai are completely different in function, structure, and transistor application scenarios so the inspiration in Lai cannot be applied to Han. The office respectfully disagrees. The general teachings of Lai of having transistors with different width-to-length ratios is merely being applied to the PAM driving circuit of Han. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Having transistors with different width-to-length ratios was well known in the art before the effective filing date of the claimed invention, and the application to the switching transistors of the PAM driving circuit of Han has the same benefit as in Lai. Although Lai is specifically for saving space in the frame area, it was well known that saving space in general, even in the pixel circuits [PAM driving circuit] was desirable when the number of transistors is increased without sacrificing performance of the circuit. Thus, the reasons for making different W/L ratios in Lai can easily be applied, by one of ordinary skill in the art, to the PAM driving circuit taught by Han.
Therefore, because of the reasons above and since none of the dependent claims are argued, the rejections of claims 1, 3-11, 15-18 and 20 are proper and maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-4, 9, 15-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2022/0101783) in view of Lai et al. (US 2022/0076604).
Regarding claim 1, Han et al. disclose a pixel driving circuit (Figure 1), comprising a pulse amplitude modulation circuit (Figure 1, 002) and a pulse width modulation circuit (Figure 1, 001) which are electrically connected to each other (Figure 1), wherein
the pulse amplitude modulation circuit (Figure 1, 002) is electrically connected to a light-emitting element (Figure 1, E) to provide a drive current to the light-emitting element (Figure 1); and the pulse amplitude modulation circuit (Figure 1, 001) is configured to control an amplitude of the drive current (Amplitude modulation controls the amplitude.), and the pulse width modulation circuit is configured to control a pulse width of the drive current (Pulse width modulation controls the pulse width.);
the pulse amplitude modulation circuit comprises a light-emitting branch connected to the light-emitting element (Figure 1, M3, M6 and M7 comprise a light-emitting branch.), and the light-emitting branch comprises a first driving transistor (Figure 1, M3), a first switching transistor (Figure 1, M6), and a second switching transistor (Figure 1, M7), wherein the first driving transistor is connected in series between the first switching transistor and the second switching transistor (Figure 1, M3, M6 and M7), a gate of the first switching transistor is connected to a first switching control terminal (Figure 1, gate of M6 is connected to EM.), a gate of the second switching transistor is connected to a second switching control terminal (Figure 1, gate of M7 is connected to EM [first=second].), and the second switching transistor is connected in series between the first driving transistor and the light-emitting element (Figure 1, M7 is in series between M3 and E.); and
the first driving transistor and the first switching transistor are double-gate double-channel transistors, and the second switching transistor is a double-gate double-channel transistor or a four-gate four-channel transistor (Figure 4 and paragraphs [0097]-[0098] explain that this is the structure for all of the transistors.).
Han et al. fail to teach wherein a width-to-length ratio of the second switching transistor is greater than a width-to-length ratio of the first switching transistor
Lai et al. disclose wherein a width-to-length ratio of a second switching transistor is greater than a width-to-length ratio of a first switching transistor (Paragraph [0061], which teaches of having different width-to-length ratios for different transistors.).
Therefore, it would have been obvious to “one of ordinary skill” in the art before the effective filing date of the claimed invention to use the width-to-length ratio teachings of Lai et al. and apply them to the first and second switching transistors in the pixel driving circuit taught by Han et al. The motivation to combine would have been in order to allocate the space occupied by each transistor according to the performance, and thus area can be saved under the premise of ensuring the performance of the circuit (See paragraph [0061] of Lai et al.).
Regarding claim 3, Han et al. and Lai et al. disclose the pixel driving circuit according to claim 1,
wherein the first switching control terminal and the second switching control terminal are a same switching control terminal (Han et al.: Figure 1 shows that both M6 and M7 are connected to EM.); or
wherein an output terminal of the pulse width modulation circuit is connected to a gate of the first driving transistor, or an output terminal of the pulse width modulation circuit is connected to a gate of the first driving transistor through a capacitor.
Regarding claim 4, Han et al. and Lai et al. disclose the pixel driving circuit according to claim 1.
Lai et al. also disclose wherein a width-to-length ratio of a first switching transistor is A1, a width-to-length ratio of the second switching transistor is A2, where A2=K x A1 (Paragraph [0061], which teaches of having different width-to-length ratios, and thus if the width-to-length ratios are different then clearly A2=K x A1.).
Han et al. and Lai et al. fail to explicitly teach wherein K>2. However, based on paragraph [0061] of Lai et al., it would have been an obvious design choice to “one of ordinary skill” in the art before the effective filing date of the claimed invention to optimize the width-to-length ratios of the first and second switching transistor. Before the effective filing date of the claimed invention, there had been a recognized problem or need in the art to adjust the width-to-length ratios of transistors of the circuit for better circuit performance. There were a finite number of identified and predictable potential width-to-length ratios of transistors based on circuit size constraints versus performance. One of ordinary skill in the art could have pursued the known potential width-to-length ratios such that K>2 since it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Regarding claim 9, Han et al. and Lai et al. disclose the pixel driving circuit according to claim 1, wherein the pulse amplitude modulation circuit further comprises a first data writing transistor connected in series between a first data signal terminal and a first electrode of the first driving transistor (Han et al.: Figure 1, M5 is a first data writing transistor connected in series between Data_A and a first electrode of M3.), and the first electrode of the first driving transistor is connected to the first switching transistor (Han et al.: Figure 1, the first electrode of M3 is connected to M6.); and the first data writing transistor is a double-gate double-channel transistor (Han et al.: Figure 4 and paragraphs [0097]-[0098] explain that this is the structure for all of the transistors.).
Regarding claim 15, Han et al. and Lai et al. disclose the pixel driving circuit according to claim 1, wherein the pulse width modulation circuit comprises an output branch comprising a second driving transistor (Han et al.: Figure 1, M14) and at least one switching transistor (Han et al.: Figure 1, M12 and M15), and the at least one transistor in the output branch is a double-gate double-channel transistor (Han et al.: Figure 4 and paragraphs [0097]-[0098] explain that this is the structure for all of the transistors.).
Regarding claim 16, Han et al. and Lai et al. disclose the pixel driving circuit according to claim 15, wherein the switching transistor in the pulse width modulation circuit comprises a third switching transistor (Han et al.: Figure 1, M12) and a fourth switching transistor (Han et al.: Figure 1, M15), the second driving transistor is connected in series between the third switching transistor and the fourth switching transistor (Han et al.: Figure 1, M14 is connected in series between M12 and M15.), a gate of the third switching transistor and a gate of the fourth switching transistor are both connected to a third switching control terminal (Han et al.: Figure 1, M12 and M15 have gates both connected to EM.), and the fourth switching transistor is connected in series between the second driving transistor and an output terminal of the pulse width modulation circuit (Han et al.: Figure 1, M15 is connected in series between M14 and the output of 001 to C2.); and the second driving transistor, the third switching transistor, and the fourth switching transistor are double-gate double-channel transistors (Han et al.: Figure 4 and paragraphs [0097]-[0098] explain that this is the structure for all of the transistors.).
Regarding claim 17, this claim is rejected under the same rationale as claim 4.
Regarding claim 18, Han et al. and Lai et al. disclose the pixel driving circuit according to claim 16, wherein the pulse width modulation circuit comprises a second data writing transistor connected in series between a second data signal terminal and a first electrode of the second driving transistor (Han et al.: Figure 1, M10 is a second data writing transistor connected in series between Data_W and a first electrode of M14.), the first electrode of the second driving transistor is connected to the third switching transistor (Han et al.: Figure 1, the first electrode of M14 is connected to M12.); and the second data writing transistor is a double-gate double-channel transistor (Han et al.: Figure 4 and paragraphs [0097]-[0098] explain that this is the structure for all of the transistors.).
Regarding claim 20, please refer to the rejection of claim 1, and furthermore Han et al. also disclose a display apparatus comprising the pixel driving circuit (Han et al.: Figure 3 and paragraph [0054]).
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2022/0101783) in view of Lai et al. (US 2022/0076604) and further in view of Zhai (US 2024/0212561).
Regarding claim 5, Han et al. and Lai et al. disclose the pixel driving circuit according to claim 1.
Han et al. and Lai et al. fail to teach wherein the light-emitting branch further comprises a third transistor connected in series between the first driving transistor and the light-emitting element, and a gate of the third transistor is connected to an output terminal of the pulse width modulation circuit.
Zhai discloses wherein a light-emitting branch further comprises a third transistor (Figure 15, T18) connected in series between the first driving transistor (Figure 15, T11) and the light-emitting element (Figure 15, light-emitting element 20), and a gate of the third transistor is connected to an output terminal of the pulse width modulation circuit (Figure 15, the gate of T18 is connected to the output of the pulse width modulation circuit 12.).
Therefore, it would have been obvious to “one of ordinary skill” in the art before the effective filing date of the claimed invention to use the pixel circuit teachings of Zhai in the pixel driving circuit taught by the combination of Han et al. and Lai et al. The motivation to combine would have been in order to better exert functions of the amplitude modulation circuit and functions of the pulse width modulation circuit, thereby improving design rationality (See paragraph [0006] of Zhai.).
Regarding claim 6, Han et al., Lai et al., and Zhai disclose the pixel driving circuit according to claim 5, wherein the third transistor (Zhai: Figure 15, T18.) is connected in series between the first driving transistor (Zhai: Figure 15, T11.) and the second switching transistor (Zhai: Figure 15, T17.); and a width-to-length ratio of the third transistor is A3, a width-to-length ratio of the first switching transistor is A1, and a width-to-length ratio of the second switching transistor is A2 (Zhai: Figure 15, T11, T17 and T18 all have width-to-length ratios.).
While Lai et al. disclose wherein a width-to-length ratio of switching transistors are different (Paragraph [0061], which teaches of having different width-to-length ratios.), Han et al., Lai et al. and Zhai fail to explicitly teach wherein A1<A3<A2. However, based on paragraph [0061] of Lai et al., it would have been an obvious design choice to “one of ordinary skill” in the art before the effective filing date of the claimed invention to optimize the width-to-length ratios of the transistors. Before the effective filing date of the claimed invention, there had been a recognized problem or need in the art to adjust the width-to-length ratios of transistors of the circuit for better circuit performance. There were a finite number of identified and predictable potential width-to-length ratios of transistors based on circuit size constraints versus performance. One of ordinary skill in the art could have pursued the known potential width-to-length ratios such that A1<A3<A2 since it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Regarding claim 7, please refer to the rejection of claim 6, Han et al., Lai et al. and Zhai fail to explicitly teach wherein the third transistor is connected in series between the second switching transistor and the light-emitting element, and where A1<A2<A3. However, it would have been an obvious design choice to “one of ordinary skill” in the art before the effective filing date of the claimed invention to locate the third transistor is connected in series between the second switching transistor and the light-emitting element, since it has been held that that shifting the position of an element is unpatentable if it would not have modified the operation of the device. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950). Further, Han et al., Zhai and Lai et al. fail to explicitly teach wherein A1<A2<A3. However, based on paragraph [0061] of Lai et al., it would have been an obvious design choice to “one of ordinary skill” in the art before the effective filing date of the claimed invention to optimize the width-to-length ratios of the transistors. Before the effective filing date of the claimed invention, there had been a recognized problem or need in the art to adjust the width-to-length ratios of transistors of the circuit for better circuit performance. There were a finite number of identified and predictable potential width-to-length ratios of transistors based on circuit size constraints versus performance. One of ordinary skill in the art could have pursued the known potential width-to-length ratios such that A1<A2<A3 since it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2022/0101783) in view of Lai et al. (US 2022/0076604) and further in view of Zhai (US 2024/0212561) and Guo et al. (US 2023/0410745).
Regarding claim 8, Han et al., Lai et al. and Zhai disclose the pixel driving circuit according to claim 7.
Han et al., Lai et al. and Zhai fail to teach wherein the third transistor is a four-gate four-channel transistor.
Guo et al. disclose wherein a transistor is a four-gate four-channel transistor (Paragraph [0062]).
Thus, the combination of Han et al., Lai et al. and Zhai and Guo et al. each disclose transistors. A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the four-gate four-channel transistor of Guo et al. could have been substituted for the third transistor of Han et al., Lai et al. and Zhai because both provide a switching operation. Furthermore, a person of ordinary skill in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing a switching operation in a pixel driving circuit.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the four-gate four-channel transistor of Guo et al. for the third transistor of Han et al., Lai et al. and Zhai according to known methods to yield the predictable result of providing a four-gate four-channel transistor.
Claims 10-11 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2022/0101783) in view of Lai et al. (US 2022/0076604) and further in view of Lim et al. (US 2016/0300526).
Regarding claim 10, Han et al. and Lai et al. disclose the pixel driving circuit according to claim 1, wherein the double-gate double-channel transistor comprises a substrate (Han et al.: Figure 4, substrate 1.), and an active layer (Han et al.: Figure 4, active layer 01.), a bottom gate, and a top gate that are located on a same side of the substrate (Han et al.: Figure 4 and paragraph [0098].).
Han et al. and Lai et al. fail to teach in a first direction, the bottom gate and the top gate are respectively located on two sides of the active layer, the bottom gate is located between the active layer and the substrate, and the first direction is perpendicular to a plane where the substrate is located; an outer edge of an orthographic projection of the bottom gate on a plane where the active layer is located is a first edge, an outer edge of an orthographic projection of the top gate on the plane where the active layer is located is a second edge, and the first edge is peripheral to the second edge.
Lim et al. disclose a double-gate double-channel transistor, wherein in a first direction, the bottom gate (Figure 4, bottom gate 1100, and paragraph [0081].) and the top gate (Figure 4, top gate 1500, and paragraph [0081].) are respectively located on two sides of the active layer (Figure 4, active layer 1300, where 1100 and 1500 are on either side of 1300 above the substrate 1000.), the bottom gate is located between the active layer and the substrate (Figure 4), and the first direction is perpendicular to a plane where the substrate is located (Figure 4); an outer edge of an orthographic projection of the bottom gate on a plane where the active layer is located is a first edge, an outer edge of an orthographic projection of the top gate on the plane where the active layer is located is a second edge, and the first edge is peripheral to the second edge (See the marked up Figure 4 below).
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Therefore, it would have been obvious to “one of ordinary skill” in the art before the effective filing date of the claimed invention to use the double-gate double-channel transistor teachings of Lim et al. for the double-gate double-channel transistor in the pixel driving circuit taught by Han et al. and Lai et al. The motivation to combine would have been in order to prevent a driving defect (See paragraphs [0004]-[0005] of Lim et al.).
Regarding claim 11, Han et al., Lai et al., and Lim et al. disclose the pixel driving circuit according to claim 10, wherein a distance between the first edge and the second edge is DO (See the marked up copy of Figure 4 of Lim et al. above.).
Han et al., Lai et al., and Lim et al. fail to teach wherein DO>1µm. However, it would have been an obvious design choice to “one of ordinary skill” in the art before the effective filing date of the claimed invention to optimize the size of DO since it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, and one of ordinary skill would have been motivated to optimize the distance dependent upon size constraints and performance to thus improve the output of the pixel circuit.
Allowable Subject Matter
Claims 12-14 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reasons for indicating allowable subject matter in claim 12 is the inclusion of the limitations reciting “wherein the pixel driving circuit comprises a first pixel driving circuit and a second pixel driving circuit, the first pixel driving circuit is configured to be electrically connected to a first color light-emitting element, the second pixel driving circuit is configured to be electrically connected to a second color light-emitting element, and a light-emitting efficiency of the first color light-emitting element is less than a light-emitting efficiency of the second color light-emitting element; and in the first pixel driving circuit, a width-to-length ratio of the first switching transistor is A11, and a width-to-length ratio of the second switching transistor is A21; and in the second pixel driving circuit, a width-to-length ratio of the first switching transistor is A12, and a width-to-length ratio of the second switching transistor is A22; where A11>A12, and/or A21>A22” which, in combination with the other recited features, is not taught and/or suggested either singularly or in combination within the prior art.
Li et al. (US 2019/0259327) generally disclose wherein transistors of different color pixels have different width-to-length ratios (See paragraphs [0060]-[0061], for example.). However, Li et al. fails to teach the specifically claimed features of claim 12 as highlighted above.
Claims 13-14 are objected to due to their dependency from claim 12.
Claim 19 is objected to for the same reasons as claim 12.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/STEPHEN G SHERMAN/Primary Examiner, Art Unit 2621
10 February 2026