DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Information Disclosure Statement
An information disclosure statement (IDS) was submitted on 11 December 2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-22 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3-12 and 15-23 of copending Application No. 18928200 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because they recite substantially similar subject matter and the limitations of the Patent/Copending Application would anticipate those of the current application as shown in the example claims in the table below.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant Application
copending Application No. 18928200
1. A storage device comprising: a volatile memory comprising a plurality of physical areas; a compression operation component configured to compress write data at a first ratio to generate first compressed data; and a control operation component configured to set the plurality of physical areas included in the volatile memory as first physical areas and second physical areas, set a first number of physical areas among the first physical areas
as first storage areas to manage the first number of physical areas in a form of a linked list, store the first compressed data in the first storage areas, and store, in the second physical areas, first logical information indicating an area set as a header, among the first storage areas.
1. A storage device comprising: a volatile memory comprising a plurality of physical areas; a compression operation circuit configured to compress write data at a first rate to generate first compressed data; and a control operation circuit configured to divide the plurality of physical areas included in the volatile memory into first physical areas and second physical areas, store the first compressed data in the first physical areas, and store first logical information indicating an area storing the first compressed data, in a first selected area of the second physical areas.
2. The storage device of claim 1, wherein the compression operation circuit is configured to compress the write data at a second rate to generate second compressed data, and wherein the control operation circuit is configured to: store the second compressed data in the first physical areas; and store second logical information indicating an area storing the second compressed data, in a second selected area of the second physical areas.
3. The storage device of claim 2, wherein the control operation circuit is configured to: set some of a current number of free areas as management areas to store free area information on the free areas that are available for storing data, among the first physical areas; and manage the management areas in a form of a linked list.
9. The storage device of claim 8, wherein, when all information stored in a first management area set as a header in a form of a linked list, among the management areas, is invalidated, the control operation circuit is configured to: set, as a new header, a second management area set as a next in the first management area; switch the first management area into the free area; and put the free area into the free area information.
A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. see MPEP § 804
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Geng (US 20230236979 A1) in view of Dye (US 6523102 B1).
Referring to claims 1 and 12, taking claim 1 as exemplary, Geng teaches
A storage device comprising: a volatile memory comprising a plurality of physical areas; ([Geng 0062-0063, Fig. 1] The system also includes a memory controller 114 for accessing a main, external memory (e.g., double rate dynamic random access memory (DRAM), sometimes called DDR). The processor-based system 100 includes a system memory 112 that includes a compressed data region configured to store data in memory entries (which may be memory lines) in compressed form. For example, the system memory 112 may include a double data rate (DDR) static random access memory (SRAM). Providing the ability to store compressed data in a compressed data region (e.g., blocks 202, 204, 206) increases memory capacity of the processor-based system 100 over physical memory size of the system memory 112.) and a control operation component configured to set the plurality of physical areas included in the volatile memory as first physical areas and second physical areas, ([Geng 0020, 0063, Fig. 2A] The compressed memory system includes a memory partitioning circuit configured to partition a memory region into a plurality of data regions. The compressed memory system also includes a compression circuit configured to compress. Providing the ability to store compressed data in a compressed data region (e.g., blocks 202, 204, 206) increases memory capacity of the processor-based system 100 over physical memory size of the system memory 112. In some implementations, the processor 104 uses virtual addressing. A virtual-to-physical address translation is performed to effectively address the compressed data region without being aware of the compression system and compression size of the compressed data region.) set a first number of physical areas among the first physical areas as first storage areas to manage the first number of physical areas ([Geng 0068, Fig. 2A] If a new memory block is needed to store the compressed data region for the evicted cache entry, the compress circuit recycles a pointer to the current memory block in the compressed memory system 200 associated with the virtual address of the evicted cache entry to one of free memory lists (e.g., list of free 64B blocks 216, list of free 48B blocks 218, list of free 32B blocks 220, and list of free 16B blocks 222) of pointers to available memory blocks in the compressed data region. The compress circuit then obtains the pointer from one of the free memory lists to the new, available memory block of desired memory block size in the compressed data region to store the compressed data region for the evicted cache entry.) store the first compressed data in the first storage areas, ([Geng 0063, Fig. 2A] Providing the ability to store compressed data in a compressed data region (e.g., blocks 202, 204, 206) increases memory capacity of the processor-based system 100 over physical memory size of the system memory 112. For example, as shown in FIG. 1, the compress circuit may be configured to compress 64-byte (64B) data words down to 48-byte (48B) compressed data words, 32-byte (32B) compressed data words, or 16-byte (16B) compressed data words, which can be stored in respective memory blocks 202(64B), 204(48B), 206(32B), and 204(16B), each having a smaller size than each of the entire memory entries of the system memory 112.) and store, in the second physical areas, first logical information indicating an area set as a header, among the first storage areas ([Geng 0065, 0071, Fig. 2A] the compressed memory system 200 includes a register file 208 that holds base pointers for the blocks 202, 204, and 206, and the metadata circuit 210 provides offsets from the base pointers for the blocks. the compression circuit provides the virtual address for the memory read request to a metadata circuit 210 that contains metadata in corresponding metadata entries for all virtual address space in the processor-based system 100. Thus, the metadata circuit 210 can be linearly addressed by the virtual address of the memory read request. The metadata is used to access the correct memory entry of the memory entries in the compressed data region for the memory read request to provide the corresponding compressed data region to the decompress circuit.).
Geng does not explicitly disclose in a form of a linked list and a compression operation component configured to compress write data at a first ratio to generate first compressed data. Geng does disclose the compressed memory system also includes a compression circuit configured to compress ([Geng 0020]).
Dye teaches in a form of a linked list ([Dye col 32:33-50, col 33:1-35, Fig. 17] each cache entry 804 may include additional linked-lists of pointers, a cache tree node free-list, a linked-list of all unused cache tree nodes 806, may be maintained. a cache entry header free-list, a linked-list of all unused cache entry headers 808. A cache entry header 808 may look something like this: struct SCacEntry {bState, bNumCacBlks, pCacBLkPtr}) a compression operation component configured to compress write data at a first ratio to generate first compressed data ([Dye col 22:33-55, col 25:1-40, col 32:33-50] The compressed cache, for example, may be allocated 1000 pages of physical memory. If the compressed cache provides a 2:1 compression ratio, then the compressed cache provides 2000 pages of effective space. For example, steps 1, 2, and 4 may complete in one-fourth the time if the compression ratio of the page is 4:1 due to the movement of compressed data. As a reference, assuming a 2:1 compression ratio, the cache structure shown in FIG. 17 preferably takes up about 2% of the compressed cache.).
Geng and Dye are analogous art because they are from the same field of endeavor in storage systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Geng and Dye before him or her to modify the system of Geng to include the linked lists and compression ratios of Dye, thereafter the system is connected to linked lists and compression ratios. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the system have more ability to adjust space saving configurations and data element organization as suggested by Dye. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Geng with Dye to obtain the invention as specified in the instant application claims.
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 2 and 13, taking claim 2 as exemplary, Geng in view of Dye teaches
The storage device of claim 1, wherein the compression operation component is configured to compress the write data at a second ratio to generate second compressed data, ([Dye col 22:33-55, col 25:1-40, col 32:33-50] The compressed cache, for example, may be allocated 1000 pages of physical memory. If the compressed cache provides a 2:1 compression ratio, then the compressed cache provides 2000 pages of effective space. For example, steps 1, 2, and 4 may complete in one-fourth the time if the compression ratio of the page is 4:1 due to the movement of compressed data. As a reference, assuming a 2:1 compression ratio, the cache structure shown in FIG. 17 preferably takes up about 2% of the compressed cache.) and wherein the control operation component is configured to set a second number of physical areas among the first physical areas as second storage areas to manage the second number of physical areas ([Geng 0063, 0068, Fig. 2A] Providing the ability to store compressed data in a compressed data region (e.g., blocks 202, 204, 206) increases memory capacity of the processor-based system 100 over physical memory size of the system memory 112. For example, as shown in FIG. 1, the compress circuit may be configured to compress 64-byte (64B) data words down to 48-byte (48B) compressed data words, 32-byte (32B) compressed data words, or 16-byte (16B) compressed data words, which can be stored in respective memory blocks 202(64B), 204(48B), 206(32B), and 204(16B), each having a smaller size than each of the entire memory entries of the system memory 112.) in a form of a linked list, ([Dye col 32:33-50, col 33:1-35, Fig. 17] each cache entry 804 may include additional linked-lists of pointers, a cache tree node free-list, a linked-list of all unused cache tree nodes 806, may be maintained. a cache entry header free-list, a linked-list of all unused cache entry headers 808. A cache entry header 808 may look something like this: struct SCacEntry {bState, bNumCacBlks, pCacBLkPtr}) store the second compressed data in the second storage areas([Geng 0063, Fig. 2A] Providing the ability to store compressed data in a compressed data region (e.g., blocks 202, 204, 206) increases memory capacity of the processor-based system 100 over physical memory size of the system memory 112. For example, as shown in FIG. 1, the compress circuit may be configured to compress 64-byte (64B) data words down to 48-byte (48B) compressed data words, 32-byte (32B) compressed data words, or 16-byte (16B) compressed data words, which can be stored in respective memory blocks 202(64B), 204(48B), 206(32B), and 204(16B), each having a smaller size than each of the entire memory entries of the system memory 112.) and store, in the second physical areas, second logical information indicating an area set as a header, among the second storage areas ([Geng 0065, 0071, Fig. 2A] the compressed memory system 200 includes a register file 208 that holds base pointers for the blocks 202, 204, and 206, and the metadata circuit 210 provides offsets from the base pointers for the blocks. the compression circuit provides the virtual address for the memory read request to a metadata circuit 210 that contains metadata in corresponding metadata entries for all virtual address space in the processor-based system 100. Thus, the metadata circuit 210 can be linearly addressed by the virtual address of the memory read request. The metadata is used to access the correct memory entry of the memory entries in the compressed data region for the memory read request to provide the corresponding compressed data region to the decompress circuit.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
The same motivation that was utilized for combining Geng and Dye as set forth in claim(s) 1 and 12 is equally applicable to this/these claim(s).
Allowable Subject Matter
Claims 3-11 and 14-22 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Regarding memory compression and linked-lists.
US 20240054079 A1
US 10999223 B1
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/FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132
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