DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
This application is a continuation in part of U.S. application No. 18/963497, filed on 11/28/2024.
Claim Objections
Claims 2-10 and 12-19 are objected to because of the following informalities: All “An apparatus according” of claims 2-10 and 12-19 should correct as – The apparatus according --; and claim 11 is missing. Appropriate correction is required.
Claims 2 and 7 are objected to under 37 CFR 1.75(c) as being in improper form because a multiple dependent claim 1. See MPEP § 608.01(n). Accordingly, the claim 7 has not been further treated on the merits.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-8, 10, 12-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Shinsato et al. [US 2013/0050955], in view of Paul et al. [US 2012/0151112].
Regarding claim 1, Shinsato et al., disclose an apparatus (100, figures 1-6), comprising:
a housing (100, figure 1) having a front panel, a top and a bottom (figure 1);
a plurality of first cards (each storage device includes a printed circuit board with an edge connector that couples a corresponding connector 400 of a second circuit board 200, figures 5-6) provided vertically in the housing adjacent the front side of the housing, such that each of the plurality of first cards is oriented at a first angle relative to the front panel, the first angle is in a range from -60° to 60°;
a plurality of module cages (202.1 and/or 202.2, figures 2-3), each of which being attached to a respective one of the plurality of first cards;
a plurality of first connectors (a plurality of edged connectors disposed at the end portions of a plurality of modules 106, figures 5-6) being electrically connected to the plurality of first cards;
a second card (200, figures 2-6) provided vertically in the housing, such that the second card is oriented at a second angle relative to the front panel, the second angle is in a range of -60° to 60°;
a plurality of second connectors (400, figures 4-6) being operable to electrically connect the plurality of first cards to the second card; and
a plurality of heat transfer elements (204.1 and/or 204.2, figures 1-3) being operable to transfer heat away from a plurality of interface modules when each of the plurality of interface modules is provided in a respective one of a plurality of module cages (figures 2-3), wherein the plurality of module cages (202.1 and/or 202.2, figures 2-3) are arranged to be non-overlapping with the second card (figures 2-3).
Shinsato et al., disclose the claimed invention except for the second card includes a processor.
Paul et al., disclose a computer system (100, figures 1-4) comprising a backplane (102, figure 1), wherein the backplane includes at least one processor (106/406, figures 1 and 4) thereon.
It would have been to one of ordinary skill in the art at the time the invention was made to add a processor thereon a second card of an apparatus of Shinsato et al., as suggested by Paul et al., in order to setup into an active backplane of the electronic apparatus.
Regarding claims 2 or 7, Shinsato et al., in view of Paul et al., further disclose wherein the plurality of interface modules being operable to transmit a first plurality of optical signals (first plurality of optical signals are transferred from a plurality of optical disk drives 106, figures 5-6, paragraph 0016) and receive a second plurality of optical signals (a second plurality of optical signals received from the second card 200, figures 5-6), wherein the plurality of module cages being operable to accommodate a plurality of interface modules (figures 5-6).
Regarding claim 3, Shinsato et al., disclose the claimed invention except for wherein the second card includes an integrated circuit.
Paul et al., further disclose wherein the backplane includes an integrated circuit (410, figures 4, paragraph 0025).
It would have been to one of ordinary skill in the art at the time the invention was made to use an integrated circuit thereon a second card of an apparatus of Shinsato et al., as suggested by Paul et al., in order to actively manage and maintain signal integrity as data travels across an integrated circuit in the apparatus.
Regarding claim 6, Shinsato et al., in view of Paul et al., further disclose wherein each of the plurality of heat transfer elements includes an air-cooled heat sink (a plurality of holes 204.1 and 204.2 provide air-cooled functionality of a heat sink, figures 3-4).
Regarding claim 8, Shinsato et al., disclose the claimed invention except for wherein the processor includes a switch.
Paul et al., further disclose wherein the processor includes a switch (figures 1 and 4, paragraph 0010).
It would have been to one of ordinary skill in the art at the time the invention was made to include a switch within a processor of an apparatus of Shinsato et al., as suggested by Paul et al., in order to improve smooth multitasking signals on the electronic apparatus.
Regarding claim 10, Shinsato et al., disclose the claimed invention except for wherein the processor includes a graphics processing unit (GPU).
Paul et al., further disclose wherein the processor includes a graphic processing unit (a graphic unit is mounted on a socket 422, figure 4).
It would have been to one of ordinary skill in the art at the time the invention was made to use a processor including a graphic processing unit in the apparatus of Shinsato et al., as suggested by Paul et al., in order to accelerate graphical tasks in the electronic apparatus.
Regarding claims 12-13, Shinsato et al., disclose the claimed invention except for wherein the processor includes an application specific integrated circuit (ASIC), and wherein the ASIC is a switch ASIC.
Paul et al., further disclose wherein the processor includes an application specific integrated circuit (ASIC, paragraph 0025).
It would have been to one of ordinary skill in the art at the time the invention was made to use a processor including a graphic processing unit in the apparatus of Shinsato et al., as suggested by Paul et al., in order to achieve superior speed, maximum power efficiency and reduce a thickness of a processor in electronic apparatus.
Regarding claim 14, Shinsato et al., disclose the claimed invention except for wherein the switch ASIC includes a first integrated circuit, the first card package further including a plurality of second integrated circuits.
Paul et al., further disclose wherein the switch ASIC includes a first integrated circuit, the first card package further including a plurality of second integrated circuits (a plurality of integrated circuits disclosed within an information handling system 400, figure 4, paragraph 0027).
It would have been to one of ordinary skill in the art at the time the invention was made to use a processor including a graphic processing unit in the apparatus of Shinsato et al., as suggested by Paul et al., in order to improve smooth multitasking signals on the electronic apparatus.
Regarding claim(s) 15 or 16, Shinsato et al., in view of Paul et al., disclose wherein the front panel of the housing includes a plurality of module cages arranged in a two-dimensional array, each of the plurality of module cages being configured to accommodate a respective one of the plurality of interface modules (figures 2-3).
Regarding claim 17, Shinsato et al., in view of Paul et al., disclose wherein each of the plurality of interface modules is a pluggable module (figures 2-4).
Regarding claim 19, Shinsato et al., in view of Paul et al., disclose wherein each of the plurality of second connectors (400, figure 4) is a low-profile connector.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Shinsato et al., in view of Paul et al., as applied to claim 1 above, and further in view of Selvidge et al. [US 2020/0367387].
Regarding claims 4-5, Shinsato et al., in view of Paul et al., disclose the claimed invention except for wherein each of the plurality of heat transfer elements includes a cold plate.
Selvidge et al., disclose an apparatus (10, figures 1-6) comprising at least one heat transfer element(s)(72, figures 3-4) includes a cold plate, wherein the cold plate is configured to be liquid-cooled (paragraphs 0015, 0025 and 0034), and wherein the heat transfer element is attached with a disk drive (20, figures 1-4) within the apparatus.
It would have been to one of ordinary skill in the art at the time the invention was made to add a heat transfer element to each disk drive in an apparatus of Shinsato et al., in view of Paul et al., as suggested by Selvidge et al., in order to provide effective heat dissipation from electronic apparatus cage.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Shinsato et al., in view of Paul et al., as applied to claim 1 above, and further in view of LIN TSE MIN [JP-2016081227].
Regarding claim 9, Shinsato et al., in view of Paul et al., disclose the claimed invention except for wherein the processor includes a network processing unit (NPU).
LIN TSE MIN, discloses an apparatus (1, figures 1-6) comprising at least one processor (figures 2, 4 and 6) being used therein, wherein the processor includes a network processing unit (NPU).
It would have been to one of ordinary skill in the art at the time the invention was made to use a processor having a functionality of network processing unit, and/or high performance computing in an apparatus of Shinsato et al., in view of Paul et al., as suggested by LIN TSE MIN, in order to handle superior speed and multiple data streams simultaneously in the electronic device.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Shinsato et al., in view of Paul et al., as applied to claim 2 above, and further in view of Bross et al. [US 2022/0012206].
Regarding claim 18, Shinsato et al., in view of Paul et al. disclose the claimed invention except for wherein each of the plurality of interface modules is compliant with an OSFP standard.
Bross et al., disclose a network/link adaptor card (211, figure 2) comprising at least one OSFP connector(s) (paragraph 0017) thereon.
It would have been to one of ordinary skill in the art at the time the invention was made to use OSFP connector in an apparatus of Shinsato et al., in view of Paul et al., as suggested by Bross et al., in order to transfer high-speed signal integrity in the electronic device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hillbrink [US 5,343,358] discloses apparatus for cooling electronic devices;
Roscoe et al. [US 6,498,731] disclose system for protecting electronic components;
Shearman et al. [US 2005/0074990] disclose optics pack;
Lin et al. [US 7,035,111] disclose circuit board orientation with different width portions;
Pritchett [US 7,075,796] discloses cage for printed circuit board;
SO et al. [US 2015/0055301] disclose card-type electronic components;
LONG et al. [US 2020/0025641] disclose leak-detachable liquid-heat-transmission device; and
Clark et al. [US 2023/0413474] disclose information handling system.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hung S. Bui whose telephone number is (571)272-2102. The examiner can normally be reached on M-F: 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allen L. Parker can be reached on (303) 297-4722. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov.
Visit https://www.uspto.gov/patents/apply/patent-center.
for more information about Patent Center and
https://www.uspto.gov/patents/docx for information about filing in DOCX format.
For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUNG S. BUI/
Primary Examiner
Art Unit 2841
/HUNG S. BUI/Primary Patent Examiner, 2841/2800
Prosecution Insights