DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Specie VIII (Figure 9) in the reply filed on 05/05/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Applicant indicates that claims 1-3, 5-9 and 12-13 are readable on the elected Specie VIII (Figure 9). Applicant also withdrawn claims 4, 10 and 11.
Priority
In the Application Data Sheet filed on 12/12/24, applicant claims for foreign priority under 35 U.S.C. 119 (a)-(d) to TW 113145358 filed on November 25, 2924. This is an error because the year “2924” is not correct. Thus, applicant claims for foreign priority under 35 U.S.C. 119 (a)-(d) to “TW 113145358 filed on November 25, 2924” is not granted. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-9 and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Springett (US 2017/0104482).
For claim 1, Figure 2A of Springett teaches a switching circuit comprising: a first transistor (Q1), which is a compound junction transistor (JFET Q1); a second transistor (Q4), which is an enhancement-mode MOS transistor (MOS transistor Q4); the first transistor (Q1) and the second transistor (Q4) being connected in series between a first terminal (DRAIN) and a second terminal (SOURCE) of the switching circuit, for controlling conduction and cutoff between the first terminal and the second terminal; a first gate voltage (voltage at gate G of Q1) for controlling a gate of the first transistor (Q1); a second gate voltage (voltage at gate G of Q4) for controlling a gate of the second transistor (Q4); and a level-shifting circuit (D2, R1, C6, D3) for generating the first gate voltage (voltage at gate G of Q1) based on a pre-control voltage (voltage at gate G of Q4 in Figure 2A) associated with the second gate voltage (voltage at gate G of Q4).
For claim 2, Figure 2A of Springett teaches wherein a breakdown voltage of the first transistor (Q1) is higher than a breakdown voltage of the second transistor (Q4), (see par. [0050]-[0051], high voltage device Q1 and low voltage device Q4).
For claim 3, Figure 2A of Springett teaches the switching circuit configured in one of the following arrangements:
arrangement A: when the second gate voltage (voltage at gate G of Q4) is controlled to an enabled state (voltage at gate G of Q4 that turns on Q4), the level-shifting circuit (D2, R1, C6, D3) shifts the pre-control voltage by a level-shift voltage (voltage drop across D2 and R1 to the gate of Q1) to generate the first gate voltage (voltage at gate G of Q1); or
arrangement B: when the second gate voltage is controlled to an enabled state, the level-shifting circuit switches the first gate voltage to a supply voltage based on the pre-control voltage, wherein the supply voltage is higher than a source voltage of the second transistor.
For claim 5, the limitations “wherein, in arrangement B:the pre-control voltage corresponds to the second gate voltage or to a drain voltage of the second transistor” in this claim is considered to be met (by Figure 2A of Springett as discussed in claim 3 above) due to the “or” statement in claim 3 (arrangement A or arrangement B), so as long as Figure 2A of Springett teaches arrangement A, then the claim is met regardless the detail of arrangement B.
For claim 6, Figure 2A of Springett teaches wherein, in an enabled state (voltage at gate G of Q4 that turns on Q4), the level of the second gate voltage (voltage at gate G of Q4) is higher than the level of the first gate voltage (voltage at gate G of Q1, due to the voltage drop across D2 and R1 to the gate G of Q1).
For claim 7, it is seen in the operation of Figure 2A of Springett that teaches wherein: in arrangement A, in the enabled state (voltage at gate G of Q4 that turns on Q4), a level of the level- shift voltage (voltage drop across D2 and R1) is lower than a gate-to-source forward conduction voltage of the first transistor (Q1); or in arrangement B, the supply voltage is less than the gate-to- source forward conduction voltage of the first transistor.
For claim 8, Figure 2A of Springett teaches wherein the first transistor (Q1) is a silicon carbide junction field-effect transistor (SiC JFET Q1, see [0050]).
For claim 9, Figure 2A of Springett teaches wherein the first transistor (Q1) and the second transistor (Q4) are both N-type (N-type Q1 and Q4) or both P- type transistors.
For claim 12, the limitation “further comprising: a Zener diode and a conversion transistor, wherein the Zener diode provides a pre-reference voltage, which is configured to control the conversion transistor to generate the supply voltage” is considered the detail of arrangement B in claim 3 (because arrangement A does not require to generate the supply voltage), so this claim is considered to be met (by Figure 2A of Springett as discussed in claim 3 above) due to the “or” statement in claim 3 (arrangement A or arrangement B), so as long as Figure 2A of Springett teaches arrangement A, then the claim is met regardless the detail of arrangement B.
For claim 13, Figure 2A of Springett teaches wherein, during transitions to the enabled state (the turn-on of Q4) and the disabled state (the turn-off of Q4), the first gate voltage (voltage at gate G of Q1) is delayed relative to the second gate voltage (voltage at gate G of Q4) by a time difference (delay through the level-shifting circuit D2, R1, C6 and D3).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Randolph et al. (Figure 4B) disclose a switching circuit comprising JFET 203 and MOSFET 202.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-7101. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2836
Prosecution Insights