DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in response to the amendment filed on 07/17/26 and the interview on 08/31/26.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5, 7 and 13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. In particularly, the specification has failed to describe the switching circuit (as amended in claim 1) “wherein the pre-control voltage corresponds to the second gate voltage” as recited in claim 5; the switching circuit (as amended in claim 1) “wherein the supply voltage is less than a gate-to-source forward conduction voltage of the first transistor” as recited in claim 7; and the switching circuit (as amended in claim 1) “wherein during transitions to the enabled state and to a disabled state, the first gate voltage is delayed relative to the second gate voltage by a time difference”. It is noted that claim 1, as amended, is drawn to Figure 9; however, Figure 9 only discloses the pre-control voltage corresponds to a drain voltage Vd2 of the second transistor M2 (i.e., Figure 9 does not disclose “the pre-control voltage corresponds to the second gate voltage” because Figure 9 discloses and shows the pre-control voltage corresponds to a drain voltage Vd2 of the second transistor M2). Similarly, for claim 7, Figure 9 does not disclose “the supply voltage is less than a gate-to-source forward conduction voltage of the first transistor" as it is disclosed in the specification in paragraph [0048] for Figure 8. Furthermore, for claim 13, "the first gate voltage is delayed relative to the second gate voltage by a time different" is disclosed in Figures 3 and 4A-4B (as it shows first gate voltage VG1 is delayed by the delay circuit 20 or 23 from the second gate voltage VG2) with the timing diagram for the delay is shown in Figure 5.
Allowable Subject Matter
Claims 1, 2, 6, 8 and 9 are allowed. The following is an examiner’s statement of reasons for allowance:
Claim 1, as amended, is allowed because applicant’s argument is found persuasive that amendment of claim 1 overcome the closet prior art, Springett (US 2017/0104482, Figure 2A), that was applied in the Non-Final Office Action, i.e., the closet prior art, Springett (US 2017/0104482, Figure 2A), fails to teach or suggest the limitations “a level-shifting circuit for generating the first gate voltage based on a pre-control voltage associated with the second gate voltage, wherein, when the second gate voltage is controlled to an enabled state, the level-shifting circuit switches the first gate voltage to a supply voltage based on the pre-control voltage, wherein the supply voltage is higher than a source voltage of the second transistor; and a Zener diode and a conversion transistor, wherein the Zener diode provides a pre-reference voltage, and wherein the pre-reference voltage is configured to control the conversion transistor to generate the supply voltage” in combination with other limitations as recited in the claim.
Claims 2, 6, 8 and 9 are allowed because they depend on claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments filed on 07/17/26 have been considered but are moot in view of the new ground of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-7101. The fax number for this group is (571) 273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
/Long Nguyen/
Primary Examiner
Art Unit 2836
Prosecution Insights