DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
This Office Action is sent in response to Applicant’s Communication received on 12/12/2024 for application number 18/978,286.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 3 is objected to because of the following informalities: “wherein a first circuit power density proximate to the first location is higher than a second power density circuitry proximate to the second location” (emphasis added) should read “wherein a first circuit power density proximate to the first location is higher than a second circuit power density proximate to the second location” (emphasis added). Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-8, 11-15 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Machnicki (US 2015/0326216 A1) in view of Muller et al. (US 2016/0350117 A1).
Regarding claim 1, Machnicki teaches a method for reducing power consumption of a processor core comprising:
estimating a plurality of temperatures, each temperature based on a corresponding temperature sensor of the plurality of temperature sensors (“The power management circuit may also receive temperature readings from temperature sensors located on the IC (block 510)… Using the values resulting from applying the temperature offsets to the temperature readings, maximum and minimum temperature values may be determine (block 520).” Par 0038) [the power management circuit estimated temperature limits by determining offset to data collected from the temperature sensors];
determining a plurality of voltage candidates, each voltage candidate based on a corresponding temperature of the plurality of temperatures, a performance target for the processor core, and a mapping of temperature to voltage margin (“The voltage offset values may be based at least in part on current or expected performance state of the processor.” Par 0030 and “A spread between the minimum and maximum temperatures may be determined, and a group of pertinent voltage offsets may be determined from this spread [between temperatures].” Par 0031 and “FIG. 4 is a diagram illustrating one embodiment of a table stored in a memory of a power management circuit for an IC embodiment, the table being used in selection of a voltage offset.” Par 0032 and “the power management circuit includes a memory configured to store a table having a plurality of entries, wherein each of the plurality of entries includes a minimum temperature range value, a maximum temperature range value, and a minimum voltage offset value” claim 4 and Figure 4) [the PMC determines voltage candidates (final offset Figure 4) by correlating detected temperature regions with performance based margins which are stored in a temperature-to-voltage mapping table], wherein the mapping includes a direct temperature-to-voltage mapping for a first range of performance targets and an inverse temperature-to-voltage mapping for a second range of performance targets (“the temperature-voltage curve is inverted in that at the lowest and highest temperatures, the minimum safe operating voltages are higher than those in the middle of the curve.” Par 0025 and Figure 2) [based on the curve shown in Figure 2, the inverted curve has a region where voltage decreases as temperature increases from the lowest range (inverse mapping in a second range: region 1 Figure 2) and increase as temperature rises in the highest range (direct mapping in a first range; region 3 Figure 2)];
selecting a core voltage based on a maximum of the voltage candidates (“Comparator 32 may determine the minimum voltage offset value from the group of pertinent voltage offsets, and provide this value to subtractor 33. The minimum voltage offset may then be subtracted from a requested operating voltage value (Requested Voltage), and the resulting value may be output as the operating voltage.” Par 0031 and “The operating voltage may then be set at a voltage that is equal to the requested operating voltage minus the voltage offset value.” Par 0023) [selecting minimum offset results in selecting maximum operating voltage because final voltage is calculated by subtracted offset from the base voltage; choosing the smallest reduction ensures the processor is receiving the highest required voltage to maintain operation in the temperature range]; and
controlling a voltage supplied to the processor core based on the selected core voltage (“Power management circuit 16 may include an adjustable voltage regulator or other circuit that enables adjustment of this voltage, which may then be supplied to functional circuit 18 as Vdd.” Par 0021).
However, Machnicki does not explicitly teach a processor core including a plurality of temperature sensors positioned at a corresponding plurality of locations within the processor core.
In the analogous art, Muller teaches a processor core including a plurality of temperature sensors positioned at a corresponding plurality of locations within the processor core (“each logic unit within the processor core may have associated therewith one or more temperature sensors in order to independently monitor temperature of that logic unit within the particular processor core.” Par 0046 and par 79, Figures 2, 6) [Figure 6 shows thermal sensors 621 placed in different locations within processor core 606].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Machnicki and Muller before him before the effective filing date of the claimed invention, to have modified Machnicki to incorporate the teachings of Muller to include temperature sensors in multiple locations within the core to predict heating trends to implement fine-grain thermal control and prevent over-heating of logic units. (Muller, paragraphs 17, 53)
Claims 8 and 15 correspond to claim 1 and are rejected accordingly.
Regarding claim 4, Machnicki and Muller teach the method of claim 1. Muller further teaches wherein the plurality of locations includes two hot locations determined likely to have a temperature higher than an average temperature of the processor core (“By adding temperature sensors to, for instance, every core logic unit, or at least every critical logic unit or every higher-heat producing logic unit … processing may be provided to create a fine-grain thermal snapshot” par 0017 and “if a particular core may be overheating in one logic unit, such as a floating point unit, then the instructions to be executed by that unit could be reordered to space out the repeating floating point instructions to that core, or the instructions could be converted to, for instance, fixed point operations to avoid the over-temperature floating point logic unit.” Par 0018) [the higher-heat producing units may overheat, so these locations are used for thermal monitoring] and one cool location determined likely to have a temperature lower than the average temperature of the processor core (“‘11’—Logic unit is cool, and may be used for instruction execution without restriction.” Par 052 and paragraph 48) [11 is a status to show a logic unit as cool and Table 1 consistently maps this status to a cache L2 circuit].
Claims 11 and 18 correspond to claim 4 and are rejected accordingly.
Regarding claim 5, Machnicki and Muller teach the method of claim 1.
Muller further teaches wherein a first temperature of the plurality of temperatures is based on a first sensor positioned proximate to integer processing circuitry, a second temperature of the plurality of temperatures is based on a second sensor positioned proximate to floating point processing circuitry, and a third temperature sensor is based on a third sensor positioned proximate to cache circuitry (“each core logic unit 619 may have at least one thermal sensor 621 associated therewith (e.g., within the footprint of the logic unit) for monitoring temperature of that logic unit” par 0079 and paragraph 48, Table 1 and Figures 2, fixed point units 218-220 (integer processing circuit), floating point execution unit 222-224, cache 204, and Figure 6).
Claim 12 and 19 correspond to claim 5 and are rejected accordingly.
Regarding claim 6, Machnicki and Muller teach the method of claim 1. Machnicki further teaches further comprising:
determining a memory circuit control parameter based on the plurality of temperatures, the performance target, and the mapping of temperature to voltage margin (“Based on the various temperature regions, a requested operating voltage, and a number of possible voltage offset values, power management circuit 16 may select a voltage offset value.” Par 0023 and : based on the temperature readings received from temperature sensors 15, power management circuitry 16 may reduce the operating voltage Vdd by a specified amount in order to recover additional voltage margin that may have been added… the voltage margin recovery method and apparatus discussed herein may be designed to function with arbitrary voltage-temperature curves.” Par 0022 and Figure 2); and
controlling a memory circuit within the processor core based on the memory circuit control parameter (“Power management circuit 16 is configured to perform various power management functions, including the controlling of the level of the voltage Vdd supplied to the functional circuitry 18.” Par 0020 and “may include … various types of memory (e.g., registers, random access memory),” par 0018 and Figures 2, 4) [the voltage offset value may correspond to the control parameter derived from the sensor readings, performance state (workload/ memory access) and temperature-voltage curves (mapping) to control Vdd supplied to the functional units which include memory circuits].
Claim 13 corresponds to claim 6 and is rejected accordingly.
Regarding claim 7, Machnicki and Muller teach the method of claim 1. Machnicki further teaches wherein the estimating of a first temperature of the plurality of temperatures includes adding a first offset to a measurement from a first temperature sensor, wherein the first offset is associated with the location within the processor core corresponding to the first temperature sensor (“In a first adder 30, the temperature reading from Sensor 0 may be combined with a first maximum offset (Temp 0 Max Offset). The temperature reading from Sensor 1 may be provided to a second adder 30, and combined with a second maximum offset (Temp 1 Max Offset). It should be noted that the offset values may be positive or negative.” Par 0028 and “an integrated circuit (IC) includes first and second temperature sensors at first and second locations of the IC” Par 0006 and “The temperature sensors may be located in different areas. Since the temperature sensors may be uncalibrated, temperature offset values may be applied to the temperature readings (block 515). Using the values resulting from applying the temperature offsets to the temperature readings, maximum and minimum temperature values may be determine (block 520).” Par 0038).
Claim 14 corresponds to claim 7 and is rejected accordingly.
Regarding claim 20, Machnicki and Muller teach the system of claim 15. Machnicki further teaches wherein the mapping of temperature to voltage margin is based on a table (paragraph 22 and Figure 4, table 40), and the selected core voltage is based on an interpolation of two voltages in the table (“In Regions 1, 2, and 3, the Vmax and Vmin voltages, after adjustment, are less than the nominal Vmax and Vmin voltages, respectively. Thus, in these regions, the operating voltage may be reduced from one of the nominal values to a corresponding one of the adjusted values, or at a value therebetween.” Par 0026).
Claims 2, 9, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Machnicki and Muller in view of Wells et al. (US 2012/0159216 A1).
Regarding claim 2, Machnicki and Muller teach the method of claim 1. However, Machnicki and Muller do not explicitly teach further comprising: determining a baseline voltage based on the performance target; wherein each of the plurality of voltage candidates is a voltage margin, and the core voltage is selected as the baseline voltage + a maximum of the voltage candidates.
In the analogous art, Wells teaches determining a baseline voltage based on the performance target (“the thresholds define a minimum voltage that should be applied to the processor in order for the processor to operate at a given frequency and temperature.” Par 0028) [minimum voltage corresponds to the baseline voltage];
wherein each of the plurality of voltage candidates is a voltage margin, and the core voltage is selected as the baseline voltage + a maximum of the voltage candidates (“controller 110 determines the final voltage required based on a baseline Vmin and inverse temperature dependence adjustment for transistor speed and processor array voltage separately, and then chooses the higher of those two as the final voltage for processor 140.” Par 0023 and “the controller determines separate voltage adjustment values for each of the plurality of internal limits of the processor and chooses a single voltage adjustment from among the separate voltage adjustment values” claim 4) [the system calculates a baseline voltage and thermal adjustments for different constraints, then applies the highest required adjustment to ensure the final core voltage satisfies the most restrictive limit].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Machnicki, Muller and Wells before him before the effective filing date of the claimed invention, to have modified Machnicki and Muller to incorporate the teachings of Wells to determine a baseline voltage and add a maximum of the voltage candidate to the baseline voltage to satisfy the most restrictive constraint on the system and still conserve energy supplied to the processor. (Wells, paragraph 23)
Claims 9 and 16 correspond to claim 2 and are rejected accordingly.
Claims 3, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Machnicki and Muller in view of Clark et al. (US 2024/0103591 A1).
Regarding claim 3, Machnicki and Muller teach the method of claim 1. However, Machnicki and Muller do not explicitly teach wherein at least one of the plurality of temperatures is based on a high-temperature sensor positioned at a first location within the processor core and at least one of the plurality of temperatures is based on a low-temperature sensor positioned at a second location within the processor core, wherein a first circuit power density proximate to the first location is higher than a second power density circuitry proximate to the second location.
In the analogous art, Clark teaches wherein at least one of the plurality of temperatures is based on a high-temperature sensor positioned at a first location within the processor core and at least one of the plurality of temperatures is based on a low-temperature sensor positioned at a second location within the processor core, wherein a first circuit power density proximate to the first location is higher than a second power density circuitry proximate to the second location (“the first thermal sensor and the second thermal sensor are positioned at first and second portions of a core of the processor.” Par 0016 and “predict a temperature of a hotspot on the processor based on the first temperature measurement and the second temperature measurement” par 0012 and “the system manager 112 also monitors activity (e.g., processing and/or localized power density) associated with one or more logical units, and uses this information when predicting a location and/or temperature of a thermal hotspot.” Par 0044 and “locations of various logic units in the system 100 that produce more heat than other portions of the system.” par 0044 and Figure 2, sensors 204 and 206 are placed at different locations relative to a hotspot 208) [a hotspot 208 is closer to the location of sensor 204 then the location of sensor 206].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Machnicki, Muller and Clark before him before the effective filing date of the claimed invention, to have modified Machnicki and Muller to incorporate the teachings of Clark to use temperature sensors at different locations relative to a hotspot to determine the location of the hotspot, take corrective actions and increase performance (overclocking) of the system. (Clark paragraph 45)
Claims 10 and 17 correspond to claim 3 and are rejected accordingly.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Duberstein et al. (US 2006/0161375 A1) teaches a method for optimizing processing speed based on measured temperatures by increasing processor core speeds if the temperatures fall below a threshold and decreasing processor core speeds if the temperatures exceed a threshold. The temperatures are measured by sensors within the core. See Figure 4.
Rusu et al. (US 2004/0037346 A1) teaches an apparatus for thermal management where processor cores contain a number of thermal sensors which provide data regarding the temperatures of the cores and a thermal management unit monitors the data and maintains the processor core temperatures to be within a predetermined operating range.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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