Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 46 - 65 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 46, and 56 are rejected under 35 U.S.C. 102a1 as being anticipated by Bernat et al (US11880714) hereinafter Bernat.
As to claim 46, Bernat discloses a method comprising: determining one or more costs associated with processing computations of one or more model layers of a model (Fig. 2 illustrates a computing system comprising accelerator modules such as 224 to comprise said model. Module 112 is a compute selection element that enable the selection of accelerator elements based on cost, see Fig. 3, and step 330, COL. 8, lines 15 – 35); identifying, based on the one or more costs, a compute fabric region of an integrated circuit comprising a plurality of processing elements used to implement the one or more model layers based on the one or more costs (Fig. 2, where the selected accelerators are coupled in via the module 216 comprising the connecting fabric, COL. 5, lines 30 – 45); and allocating the processing computations of the one or more model layers to the compute fabric region. (Fig. 2, and module 218 that comprises the host fabric interface, COL. 5, line 47 – COL. 6, line 10).
As to claim 56, Bernat discloses a system comprising: a compute fabric (Fig. 2, and module 218 comprising a soc with the host fabric interface, COL. 5, lines 30 – 45);
and processing circuitry configured to: determine one or more costs associated with processing computations of one or more model layers of a model ( Module 112 of Fig. 2 is a compute selection element that enable the selection of accelerator elements based on cost , see Fig. 3, and step 330, COL. 8, lines 15 – 35); identify, based on the one or more costs, a compute fabric region, of the compute fabric, comprising a plurality of processing elements used to implement the one or more model layers based on the one or more costs (Fig. 2, where the selected accelerators are coupled in via the module 216 comprising the connecting fabric, COL. 5, lines 30 – 45) ; and allocate the processing computations of the one or more model layers to the compute fabric region (Fig. 2, and module 218 that comprises the host fabric interface , COL. 5, line 47 – COL. 6, line 10).
Allowable Subject Matter
Claims 47 – 55, 57 – 65 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US20210103544, US20200089535, and US11188382 among other teach the efficient management of computing resources in a machine learning system.
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/C.A.D/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184