Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 14 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11553589 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because of claim mapping below.
Instant Application
Claim 14. A printed circuit board comprising: a plurality of layers, a top layer of the plurality of layers including a conductive surface film; and via patterns formed in the plurality of layers, each of the via patterns comprising: first and second signal vias that form a differential signal pair; and at least one conductive shadow via electrically connected to the conductive surface film, wherein the at least one conductive shadow via is located between the first and second signal vias and wherein the at least one conductive shadow via contacts the conductive suiface film on opposite sides of the first and second signal vias, thereby effectively electrically short circuiting opposite sides of the conductive surface film between the first and second signal vias.
US Patent 11553589 B2
Claim 1. A printed circuit board comprising: a plurality of layers, a top layer of the plurality of layers including a conductive surface film; and via patterns formed in the plurality of layers, each of the via patterns comprising: at least one signal via connected to a layer of the plurality of layers, wherein the at least one signal via comprises first and second signal vias that form a differential signal pair; and at least one conductive shadow via electrically connected to the conductive surface film, wherein the at least one conductive shadow via includes two shadow vias located midway between the first and second signal vias and wherein the two shadow vias contact the conductive surface film on opposite sides of the first and second signal vias, thereby effectively electrically short circuiting opposite sides of the conductive surface film between the first and second signal vias.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim (s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morgan (US 8080738 B2).
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Regarding claim 1, Morgan discloses a printed circuit board (102;Fig.4) comprising :a plurality of layers including conductive layers separated by dielectric layers (102 includes a plurality of layers with dielectric layers to separate the signal conductor layers ); and a connector footprint (see connector footprint formed on 102 for connectors ;Fig.1) formed on the plurality of layers, the connector footprint comprising: a plurality of columns of pairs of signal vias (see columns of 170a-170m;Fig.4), the pairs of signal vias in adjacent columns of the plurality of columns being offset in a direction of the columns (see 170d and 170e offset with 170h and 170i) ; and ground vias (172; also see Reproduced Fig.4 above) disposed in the columns between adjacent pairs of signal vias (see plurality of 172 disposed between pairs of signal vias 170b-170c and 170d and 170e).
Regarding claim 2, Morgan discloses wherein the ground vias include at least two ground vias between adjacent pairs of signal vias (see ground vias in Reproduce Fig.4 above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim (s) 3-4, 7-9 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morgan as applied to claim 1 above, and further in view of Kawai (CN 103260340A).
Regarding claim 3 and 12, Morgan fails to specifically disclose at least one conductive shadow via located between signal vias of the pairs of signal vias.
Kawai discloses at least one conductive shadow via (see differential signal through hole 14 surrounding 12A and 12B; see Fig.1-2) located between signal vias (12A and 12B; see Fig.1 and Fig.2) of the pairs of signal vias.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Kawai to modify the device of Morgan in order to assist in improving signal integrity.
Regarding claim 4, Morgan fails to specifically disclose wherein the at least one conductive shadow via comprises two or more shadow vias.
Kawai discloses wherein at least one conductive shadow via comprises two or more shadow vias (see both 14 that surround 12A and 12B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Kawai to modify the device of Morgan in order to assist in improving signal integrity.
Regarding claim 7, Morgan fails to specifically disclose additional shadow vias located between adjacent pairs of signal vias.
Kawai discloses two or more shadow vias (see both 14 that surround 12A and 12B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Kawai to modify the device of Morgan in order to assist in improving signal integrity.
Regarding claim 8, Morgan fails to specifically disclose wherein the two or more shadow vias are equally spaced from the signal vias of the pairs of signal vias.
Kawai discloses wherein the two or more shadow vias are equally spaced from the signal vias of the pairs of signal vias (see 14 equally spaced from 12 respectively).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Kawai to modify the device of Morgan in order to assist in improving signal integrity.
Regarding claim 9, Morgan fails to specifically disclose wherein the two or more shadow vias extend through at least one layer of the plurality of layers.
Kawai discloses wherein the two or more shadow vias extend through at least one layer of the plurality of layers (see 14 in Fig.2)..
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Kawai to modify the device of Morgan in order to assist in improving signal integrity.
Claim (s) 6 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morgan as applied to claim 1 above, and further in view of Gisin et al. (US 2006/0151869 A1) hereinafter Gisin.
Regarding claim 6, Morgan is silent with respect to wherein the connector footprint further comprises a plurality of antipads; each of the pairs of signal vias is disposed within an antipad of the plurality of antipads; and the connector footprint further comprises conductive structures electrically shorting opposite sides of the antipads.
Gisin discloses a plurality of antipads (130 and 131;Fig.1) ;each of the pairs of signal vias is disposed within an antipad (see 120 in 130 and 121 in 131) of the plurality of antipads; and the connector footprint further comprises conductive structures (see 132)electrically shorting opposite sides of the antipads (see 130 and 131 being shorted by 132).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Gisin to modify the signal vias of Morgan in order to improve the signal integrity of the differential signal pairs.
Regarding claim 11, Morgan is silent with respect to wherein the connector footprint further comprises a first antipad surrounding a first signal via of respective pairs of signal vias and a second antipad surrounding a second signal via of respective pairs of signal vias.
Gisin discloses wherein the connector footprint further comprises a first antipad (130;Fig.1) surrounding a first signal via (120) of respective pairs of signal vias (120 and 121) and a second antipad (131) surrounding a second signal via (121) of respective pairs of signal vias.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Gisin to modify the signal vias of Morgan in order to improve the signal integrity of the differential signal pairs.
Allowable Subject Matter
Claims 5,10 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance:
Regarding claims 5, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the two or more shadow vias are smaller in diameter than the signal vias" in combination with the remaining limitations of the claim 1 and 4.
Regarding claim 10, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the two or more shadow vias are plated or filled with a conductive material" in combination with the remaining limitations of the claim 1 and 4.
Regarding claim 13, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" the at least one conductive shadow via has a smaller diameter than the signal vias of the pairs of signal vias." in combination with the remaining limitations of the claim 1 and 12.
Therefore, prior art of record neither anticipates nor renders obvious the instantapplication claimed invention as a whole either taken alone or in combination.
Any comments considered necessary by applicant must be submitted no laterthan the payment of the issue fee and, to avoid processing delays, should preferablyaccompany the issue fee. Such submissions should be clearly labeled "Comments onStatement of Reasons for Allowance."
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/PETE T LEE/Primary Examiner, Art Unit 2847
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