Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1, 8 and 15.
b. Claims 1-20 are pending on the application.
Drawings
2. The drawings were received on 12/12/2024. These drawings are review and accepted by examiner.
Information Disclosure Statement
3. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 03/04/2026. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 01/15/2026. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 12/12/2024. The information disclosed therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1, 5-8, 12-15 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (Pub. No.: US 2018/0218775 A1; “Kim et al”).
Regarding to independent claim 8, Kim et al in Figures 1-21 are directly discloses a memory device (a memory system 1 include a memory device 20, 100, Figures 1-3), comprising:
a memory block (a memory block BLK1…BLKZ, Fig. 2) including a plurality of memory cells (a memory cell array 22 and 160 includes a plurality of memory cells, Figs. 1-2) that are arranged in a plurality of word lines and a plurality of NAND strings (a NAND strings, block BLK, Fig. 3, paragraph 0042); and
circuitry (a memory controller 10, Fig. 1 and control logic 110, Fig. 2) that is configured to program the memory cells (the memory cell array 22 and 160) of a selected word line of the plurality of word lines to a plurality of data states in a plurality of program loops (a Pre-Pulse CNTR 24 and 114, Figs. 1-2) that include programming pulses and verify operations, during at least one of the verify operations (the Pre-Pulse CNTR 24 and 114 controller for control an operation and boosting operation may occur during a read/verify operation when a plurality of program loop for programming data to the memory cells of the memory array 22 or 160 are performed), the circuitry (a memory controller 10 and control logic 110) being configured to;
not lock out (unselect memory cells) a set of the plurality of NAND strings (block BLK, memory cell array 22, 160), the NAND strings of the set including at least some of the memory cells of the selected word line that have completed programming so that electricity is conducted through the NAND strings of the set during sensing (a Soft-Erase CNTR 26 and 116, Figs. 1-2)(for example, the soft erase cntr 26 and 116 may control a read voltage for verifying a programming state of the first memory cell to be applied to the selected word linein a first verification and further control pre-pulse to be applied to a gate of a string selected of each of a plurality of unselected memory cell strings, see at least in Figures 1-3, paragraph 0029 to paragraph 0052 and the related disclosures).
Regarding dependent claim 12, Kim et al in Figures 1-21 are directly discloses a memory device (a memory system 1 include a memory device 20, 100, Figures 1-3), wherein the set of NAND strings (a NAND strings, block BLK, Fig. 3) includes the NAND strings that are coupled with the memory cells (a memory cell array 22, 160) of all but one of the programmed data states that have completed programming (the pre-pulse controller 24 may determine a pre-pulse sending time base on a program voltage level that is being applied to the selected memory cell programming, paragraph 0035).
Regarding dependent claim 13, Kim et al in Figures 1-21 are directly discloses a memory device (a memory system 1 include a memory device 20, 100, Figures 1-3), further including a source line, and wherein during sensing, the circuitry sets the source line at approximately zero Volts (0 V)(the memory cell array 160, each of the plurality strings may be connected to a bit line to which 0V is applied for the programming, paragraph 0043).
Regarding dependent claim 14, Kim et al in Figures 1-21 are directly discloses a memory device (a memory system 1 include a memory device 20, 100, Figures 1-3), wherein during the verify operation of at least one of the program loops, the circuitry (a memory controller 10 and control logic 110) applies a verify voltage to the selected word line (the memory cell array 160, each of the plurality strings may be connected to a bit line to which 0V is applied for the programming, paragraph 0043).
Regarding to independent claim 15, Kim et al in Figures 1-21 are directly discloses an apparatus (a memory system 1 include a memory device 20, 100, Figures 1-3), comprising:
a memory block (a memory block BLK1…BLKZ, Fig. 2) including a plurality of memory cells (a memory cell array 22 and 160 includes a plurality of memory cells, Figs. 1-2) that are arranged in a plurality of word lines and a plurality of NAND strings (a NAND strings, block BLK, Fig. 3, paragraph 0042); and
a programming means (a memory controller 10, Fig. 1 and control logic 110, Fig. 2) for programming the memory cells (the memory cell array 22 and 160) of a selected word line of the plurality of word lines to a plurality of data states in a plurality of program loops (a Pre-Pulse CNTR 24 and 114, Figs. 1-2) that include programming pulses and verify operations, during at least one of the verify operations (the Pre-Pulse CNTR 24 and 114 controller for control an operation and boosting operation may occur during a read/verify operation when a plurality of program loop for programming data to the memory cells of the memory array 22 or 160 are performed), the programming means (a memory controller 10 and control logic 110) being configured to;
not lock out (unselect memory cells) a first set of the plurality of NAND strings (block BLK, memory cell array 22, 160), the NAND strings of the first set including at least some of the memory cells of the selected word line that have completed programming and conducted electricity through the first set of NAND strings and through a second set of NAND strings that including the memory cells of the selected word line that are being programmed. (a Soft-Erase CNTR 26 and 116, Figs. 1-2)(for example, the soft erase cntr 26 and 116 may control a read voltage for verifying a programming state of the first memory cell to be applied to the selected word linein a first verification and further control pre-pulse to be applied to a gate of a string selected of each of a plurality of unselected memory cell strings, see at least in Figures 1-3, paragraph 0029 to paragraph 0052 and the related disclosures).
Regarding dependent claim 19, Kim et al in Figures 1-21 are directly discloses an apparatus (a memory system 1 include a memory device 20, 100, Figures 1-3), wherein the first set of NAND strings (a NAND strings, block BLK, Fig. 3) includes the NAND strings that are coupled with the memory cells (a memory cell array 22, 160) of all but one of the programmed data states that have completed programming (the pre-pulse controller 24 may determine a pre-pulse sending time base on a program voltage level that is being applied to the selected memory cell programming, paragraph 0035).
Regarding dependent claim 20, Kim et al in Figures 1-21 are directly discloses an apparatus (a memory system 1 include a memory device 20, 100, Figures 1-3), further including a source line, and wherein during sensing, the circuitry sets the source line at approximately zero Volts (0 V)(the memory cell array 160, each of the plurality strings may be connected to a bit line to which 0V is applied for the programming, paragraph 0043).
Regarding claims 1 and 5-7, they encompass the same scope of invention as that of claims 8, 12-15 and 19-20, except they draft the invention in method format instead of apparatus format. Kim et al. teach all the necessary elements to perform the method of these claims. The aspects of the invention contained in claims 1 and 5-7, are therefore rejected in method format for the same reasons claims 8, 12-15 and 19-20, were rejected in apparatus format, as discussed above in the prior paragraphs of the office action.
Allowable Subject Matter
5. Claims 2-4, 9-11 and 16-18, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claims 2-4, the prior art fails to tech or suggest the claimed limitations, namely, the plurality of programmed data states includes a plurality of early data states that are associated with relatively low threshold voltage ranges and a plurality of later data states that are associated with relatively higher threshold voltage ranges, wherein the step of not locking out the set of NAND strings so that electricity is conducted through the set of NAND strings during sensing occurs during programming of the plurality of later data states, wherein the plurality of programmed data states includes seven programmed data states and wherein the plurality of later data states includes three of the seven programmed data states.
With respected to dependent claims 9-11, the prior art fails to tech or suggest the claimed limitations, namely, the plurality of programmed data states includes a plurality of early data states that are associated with relatively low threshold voltage ranges and a plurality of later data states that are associated with relatively higher threshold voltage ranges, wherein the circuitry is configured to not lock out the set of the plurality of NAND strings during programming of the plurality of later data states, wherein the plurality of programmed data states includes seven programmed data states and wherein the plurality of later data states includes three of the seven programmed data states.
With respected to dependent claims 16-18, the prior art fails to tech or suggest the claimed limitations, namely, the plurality of programmed data states includes a plurality of early data states that are associated with relatively low threshold voltage ranges and a plurality of later data states that are associated with relatively higher threshold voltage ranges, wherein the programming means is configured to not lock out the set of the plurality of NAND strings during programming of the plurality of later data states, wherein the plurality of programmed data states includes seven programmed data states and wherein the plurality of later data states includes three of the seven programmed data states.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hwang (US. 10,210,921) discloses non-volatile ferroelectric memory device and method of driving the same.
Xiang et al (US. 2025/0349373 A1) discloses memory device and operation method thereof.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
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/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov
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