DETAILED ACTION
This action is responsive to the following: the application filed on December 12, 2024 and the information disclosure statements filed on February 20, 2025, May 19, 2025, September 29, 2025, December 12, 2025, and May 7, 2026.
Claims 1-20 are pending. Claims 1 and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-10 and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cho eta al (US 20200142771 A1) in view of Schuette (US 20110084978 A1).
Regarding Independent Claim 1, Cho teaches a memory (Fig. 1: 10), comprising:
an interface configured to communicate with a host (Fig 1: 100); and
a memory array (Fig. 1: 200);
the memory (Fig. 1: 10) configured be accessed:
with system ECC function (Fig. 1: 130) enabled and link ECC (Fig. 1: 160) function enabled.
However, Cho fails to teach in a first mode with no link ECC and no system ECC,
in a second mode with system ECC function enabled and no link ECC.
Schuette teaches of selectively enabling (Fig. 1: ECC on) and disabling (Fig. 1: ECC off) the ECC in a host interface (Fig. 1: Memory Controller) when accessing a local memory (Fig. 1: Flush Local Memory).
In para 5-8 Schuette states that turning ECC off can improve Bandwidth and therefore improve performance for some use cases of the memory for which the tradeoff of bandwidth for error correction is worthwhile. But the error correction is still necessary for normal computing application. Thus, being able to switch between ECC on and ECC off modes is useful in improving the performance of accessing the memory.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Schuette to the teachings of Cho to produce a memory that has multiple modes of operation with different combinations of link ECC and System ECC enabled or disabled.
Regarding Claim 2, Cho and Schuette teach the limitations of claim 1. Cho further teaches wherein in the memory is configured to receive data (Fig. 2: DTA) and system ECC (Fig. 1: MSG1) from the host (para 51 “The host interface 120 receives a request REQ and data DTA from the host”).
Regarding Claim 3, Cho and Schuette teach the limitations of claim 2. Cho further teaches wherein the memory array (Fig. 3: 135) comprises a first portion and a second portion (Fig. 3: 137) and wherein the memory is further configured to store the data in the first portion (Fig. 3: 135) and the system ECC (Fig. 3: ECC1) in the second portion (Fig. 3: 137).
Regarding Claim 6, Cho and Schuette teach the limitations of claim 1. Cho further teaches the memory is configured to output data (Fig. 2: DTA) and system ECC (Fig. 2: MSG2) to the host.
Regarding Claim 7, Cho and Schuette teach the limitations of claim 6. Cho further teaches the memory array (Fig. 3: 135) comprises a first portion and a second portion (Fig. 3: 137) and wherein the memory is further configured to output the data from the first portion (Fig. 3: 135) and the system ECC (Fig. 3: ECC1) from the second portion (Fig. 3: 137).
Regarding Claim 8, is rejected for the same reasons as claim 3. the memory array comprises a first portion and a second portion and wherein the memory is further configured to output the data from the first portion and the system ECC from the second portion.
Regarding Claim 9, Cho and Schuette teach the limitations of claim 1. Cho further the memory is configured to receive (Fig. 2: 140, 170) data (Fig. 2: DTA), system ECC (Fig. 2: MSG1), and link ECC (Fig. 2: CM1) from the host.
Regarding Claim 10, is rejected for the same reasons as claims 3 and 8.
Regarding Claim 13, Cho and Schuette teach the limitations of claim 9. Cho further teaches a link ECC decoder (Fig. 2: 180) configured to detect/correct errors in the data during a write operation.
Regarding Claim 14, Cho and Schuette teach the limitations of claim 1. Cho further teaches the memory is configured to output (Fig. 2: 150, 180) data (Fig. 2: DTA), system ECC (Fig. 2: MSG2), and link ECC (Fig. 2: CM2) to the host.
Regarding Claim 15, is rejected for the same reasons as claim 7.
Regarding Claim 16, Cho and Schuette teach the limitations of claim 10. Cho further teaches further comprising a link ECC encoder (Fig. 2: 170) to generate the link ECC based on the data (Fig. 2: DTA).
Regarding Independent Claim 17, Cho teaches a host, comprising an interface (Fig 1: 100) configured to couple to a memory (Fig. 1: 200);, the host configured to access the memory:
with the system ECC function (Fig. 1: 130) enabled and a link ECC (Fig. 1: 160) function enabled.
However, Cho fails to teach in a first mode with no link ECC and no system ECC,
in a second mode with system ECC function enabled and no link ECC.
Schuette teaches of selectively enabling (Fig. 1: ECC on) and disabling (Fig. 1: ECC off) the ECC in a host interface (Fig. 1: Memory Controller) when accessing a local memory (Fig. 1: Flush Local Memory).
In para 5-8 Schuette states that turning ECC off can improve Bandwidth and therefore improve performance for some use cases of the memory for which the trade off of bandwidth for error correction is worthwhile. But the error correction is still necessary for normal computing application. Thus, being able to switch between ECC on and ECC off modes is useful in improving the performance of accessing the memory.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Schuette to the teachings of Cho to produce a memory that has multiple modes of operation with different combinations of link ECC and System ECC enabled or disabled.
Regarding Claim 18, Cho and Schuette teach the limitations of claim 17. Cho further teaches the host is configured to send to the memory (Fig. 2: 140) or receive (Fig. 2: 150) from the memory data (Fig. 2: DTA) and system ECC (Fig. 2: MSG1, MSG2).
Regarding Claim 19, Cho and Schuette teach the limitations of claim 17. Cho further teaches wherein the host is configured to send (Fig. 2: 140, 170) to the memory or receive (Fig. 2: 150, 180) from the memory data (Fig. 2: DTA), system ECC (Fig. 2: MSG1, MSG2), and link ECC (Fig. 2: CM1. CM2).
Regarding Claim 20, Cho and Schuette teach the limitations of claim 17. Schuette further teaches further configured to configure a mode register to set an operation mode of the memory (Fig. 1: Application detect, Application switch).
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 20200142771 A1) and Schuette (US 20110084978 A1) in view of Minzoni (US 20180336959 A1).
Regarding Claim 4, Cho and Schuette teach the limitations of claim 3. Cho and Schuette fail to teach wherein the first portion and the second portion have a same row address and a different column address.
Minzoni teaches wherein the first portion (Fig.3: data array) and the second portion (Fig.3: ECC array) have a same row address (Fig.3: word line) and a different column address (Fig. 3: M bit, N bit).
Inherently when dividing a 2D memory array into sub arrays either the subarrays must share common address space in the column or word direction.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Minzoni to the teachings of Cho and Schuette to produce a memory with multiple ECC modes where the ECC information is stored in a portion of the memory array that shares a common word address with the data storying array.
Regarding Claim 11, this claim is rejected for the same reasons as claim 4.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 20200142771 A1) and Schuette (US 20110084978 A1) in view of Perego (US 20120182821 A1).
Regarding Claim 5, Cho and Schuette teach the limitations of claim 3. Cho and Schuette fail to teach wherein the first portion and the second portion have a same column address and a different row address.
Perego teaches wherein the first portion (Fig. 4: DATA AREA, QUAD A1) and the second portion (Fig. 4: ECC AREA, QUAD A1) have a same column address (para 20 “In one embodiment, the data access and ECC access can have the same or different column addresses.”) and a different row address (Fig. 4: 424).
Inherently when dividing a 2D memory array into sub arrays either the subarrays must share common address space in the column or word direction.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Perego to the teachings of Cho and Schuette to produce a memory with multiple ECC modes where the ECC information is stored in a portion of the memory array that shares a common column address with the data storying array.
Regarding Claim 12, this claim is rejected for the same reasons as claim 5.\
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/Donald HB Braswell/ Primary Examiner, Art Unit 2825
Prosecution Insights