DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0268908 (Qi).
For claim 1, Qi figure 2 teaches a receiver circuit comprising:
a first stage circuit (204 and 206) configured to receive a first input differential signal through a first input terminal and a second input differential signal through a second input terminal different from the first input terminal (see, e.g., para [0020], “Examples of transmission paths that may be used in channel 110 include differential signaling paths made up of pairs of conductive wires, single conductive paths, coaxial cable paths and other transmission-line paths, paths on printed circuit boards, combinations of such paths, or other suitable communications link paths.”), and perform a waveform adjustment operation or amplification operation on the first and second input differential signals (see, specification, the paths adjust the duty cycle of the signal);
a replica circuit (the scaled down replica, 214 and 216) configured to receive a common mode voltage related to the first and second input differential signals, and perform a waveform adjustment operation or amplification operation on the common mode voltage;
a multiplexer (220) that is configured to output one of an output of the first stage circuit and an output of the replica circuit as first and second intermediate differential signals based on an offset calibration enable signal (the loop select signal from 202); and
an offset calibration logic configured to receive a digital signal generated based on the first and second intermediate differential signals, and perform an offset calibration operation based on the digital signal (see, e.g., para [0023], “ the comparator is an auto-zero comparator with built-in offset calibration.”).
Allowable Subject Matter
Claims 2-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 13-21 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art teaches the limitation of how to implement its components at a transistor level.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D HOUSTON whose telephone number is (571)270-3901. The examiner can normally be reached M-F 10-7 CST.
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/ADAM D HOUSTON/ Primary Examiner, Art Unit 2836
