DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Ahmed et al. (USPN 2020/0327843 A1) in view of Kwon et al. (KR 2021-0144403 A), further in view of Kim et al. (USPN 2022/0208115 A1).
As to claim 1, Ahmed teaches a display device comprising:
a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels (see at least fig. 2: display 205, pixels 212, 214, 216, 218, 220; figs. 6A-C: data lines 635, gate/scan lines 640, figs. 7A-B: pixels 705), wherein each of the plurality of pixels includes:
a first-first sub-pixel configured to emit a first color of light and a first-second sub-pixel configured to emit the first color of light; a second-first sub-pixel configured to emit a second color of light and a second-second sub-pixel configured to emit the second color of light; and a third-first sub-pixel configured to emit a third color of light and a third-second sub-pixel configured to emit the third color of light (see at least figs. 7A-B and [0041] “drive rows (e.g., 730a-c) of pixels in the display as well as the individual sub-pixel elements (e.g., red, green, and blue) of the array of pixels to cause corresponding graphics to be displayed. Further, redundant sets of sub-pixels may be provided to implement each pixel (e.g., 705) in the display. In this example, three redundant sets of red, green, and blue LED elements may be provided to redundantly implement each pixel (e.g., 705)”).
Ahmed does not directly teach wherein the first-first, second-first, and third-first sub-pixels and the first-second, second-second, and third-second sub-pixels are configured to be alternately driven at intervals of at least one frame period; and wherein the first-first sub-pixel and the first-second sub-pixel are connected to different data lines, the second-first sub-pixel and the second-second sub-pixel are commonly connected to one data line, and the third-first sub-pixel and the third-second sub-pixel are commonly connected to one data line.
Kwon teaches wherein two groups of subpixels are configured to be alternately driven at intervals of at least one frame period (see at least figs. 20-30: EN1 and EN2 signals drive the sub-pixel arrays AA1 SP1 and AA2 SP2 in alternating frames (F1/F3 vs F2/F4) and [0135] “the first demultiplexer (113) can alternately supply data voltages output from the output channels of the first data driving unit (111) to a plurality of data lines (61) during the active section (AT) of the driving frame period .. The second demultiplexer (114) can alternately supply data voltages output from the output channels of the second data driving unit (112) to a plurality of data lines (62) during the active section (AT) of the driving frame period”; [0144] “The MUX selection signals (MUX1, MUX) for controlling the demultiplexers (141, 142) are generated in reverse phase during the active section [ACT (Normal)] of the driving frame period, so as to alternately turn on the switch elements (M1, M2).”; [0146]-[0150] “first sub-pixel array (AA1) is driven at a frame frequency of 60 Hz and the second sub-pixel array (AA2) is driven at a frame frequency of 30 Hz” – note first sub-pixel array AA1 and second sub-pixel array AA2, each containing full color sub-pixels (SP1, SP2) - the two arrays (AA1, AA2) provide the “first” and “second” sub-pixels of the same color – see fig. 3 and “[0043] “each pixel (P) includes R, G, and B sub-pixels”).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply the alternating drive technique of Kwon to the redundant sub-pixel architecture of Ahmed. Kwon teaches that alternate-frame driving of corresponding sub-pixel arrays reduces power consumption, mitigates image sticking, and extends pixel lifetime. Ahmed provides a redundant sub-pixel configuration that is structurally suited to such time-sharing control. A person having ordinary skill in the art would have been motivated to use Kwon’s known frame-skipping and enable-signal scheme (EN1/EN2) to alternately activate Ahmed’s main and redundant sub-pixels of matching colors in successive frame intervals, yielding predictable advantages in power efficiency, uniformity, and lifetime performance. Further rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods and the combination yields nothing more than predictable results to one of ordinary skill in the art.
Kwon does not directly teach wherein the first-first sub-pixel and the first-second sub-pixel are connected to different data lines, the second-first sub-pixel and the second-second sub-pixel are commonly connected to one data line, and the third-first sub-pixel and the third-second sub-pixel are commonly connected to one data line.
Kim teaches a display device structure in which adjacent subpixels share data lines and wherein different subpixels within a unit pixel may be connected to different data lines (see at least [0008] “adjacent subpixels share data lines”; [0010] “Each of the unit pixels includes a plurality of subpixels which are connected to a first data line and a second data line. The first and second data lines are connected to the plurality of subpixels which are comprised in the unit pixel and are the same or different”; [0013] “The first subpixel and a second subpixel of the first unit pixel are connected to the first data line, and the third subpixel is connected to the second data line”; [0039] “the first one data line DL11 to DL1m can be connected to two or more subpixels sP.”; [0040] “the second one data line DL21 to DL2m can be connected to two or more subpixels sP.”; [0061]-[0064]: at least two subpixels of a unit pixel share a first data line while another subpixel is connected to a different data line and selected subpixels in adjacent unit pixels share a common data line). Kim therefore teaches or at least suggests a mixed data-line connection topology in which some corresponding subpixels share a common data line while other corresponding subpixels are connected to a different data line.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the mixed data-line connection topology of Kim into the display architecture resulting from the combination of Ahmed and Kwon. The combination would have yielded predictable results because the references each address compatible aspects of display panel design—Ahmed providing redundant sub-pixel structures, Kwon providing alternating frame driving of corresponding sub-pixel groups, and Kim providing established data-line connection schemes for sub-pixels within a unit pixel. A person having ordinary skill in the art would therefore have been motivated to adopt Kim’s known sub-pixel data-line configuration in the Ahmed/Kwon display device in order to achieve efficient wiring and driver utilization while implementing the alternating sub-pixel driving architecture.
As to claim 21, Ahmed teaches a display device comprising:
a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels (see at least fig. 2: display 205, pixels 212, 214, 216, 218, 220; figs. 6A-C: data lines 635, gate/scan lines 640, figs. 7A-B: pixels 705),
at least one of the plurality of pixels including a main group of sub-pixels having a first-first sub-pixel, a second-first subpixel and a third-first subpixel, and a redundancy group of sub-pixels having first-second sub-pixel, a second-second subpixel and a third-second subpixel (see at least figs. 7A-B and [0041] “drive rows (e.g., 730a-c) of pixels in the display as well as the individual sub-pixel elements (e.g., red, green, and blue) of the array of pixels to cause corresponding graphics to be displayed. Further, redundant sets of sub-pixels may be provided to implement each pixel (e.g., 705) in the display. In this example, three redundant sets of red, green, and blue LED elements may be provided to redundantly implement each pixel (e.g., 705)”); and
Ahmed does not directly teach a controller configured to drive the main group of sub-pixels and the redundancy group of sub-pixels in an alternating manner to display images, wherein the first-first sub-pixel and the first-second sub-pixel are configured to emit a same first color of light, the second-first sub-pixel and the second-second sub-pixel are configured to emit a same second color of light, and the third-first sub-pixel and the third-second sub-pixel are configured to emit a same third color of light.
Kwon teaches a controller configured to drive the main group of sub-pixels and the redundancy group of sub-pixels in an alternating manner to display images, wherein the first-first sub-pixel and the first-second sub-pixel are configured to emit a same first color of light, the second-first sub-pixel and the second-second sub-pixel are configured to emit a same second color of light, and the third-first sub-pixel and the third-second sub-pixel are configured to emit a same third color of light (see at least figs. 3, 20-30: EN1 and EN2 signals drive the sub-pixel arrays AA1 SP1 and AA2 SP2 in alternating frames (F1/F3 vs F2/F4) and [0043] “each pixel (P) includes R, G, and B sub-pixels as illustrated in FIG. 3.”; [0135] “the first demultiplexer (113) can alternately supply data voltages output from the output channels of the first data driving unit (111) to a plurality of data lines (61) during the active section (AT) of the driving frame period .. The second demultiplexer (114) can alternately supply data voltages output from the output channels of the second data driving unit (112) to a plurality of data lines (62) during the active section (AT) of the driving frame period”; [0144] “The MUX selection signals (MUX1, MUX) for controlling the demultiplexers (141, 142) are generated in reverse phase during the active section [ACT (Normal)] of the driving frame period, so as to alternately turn on the switch elements (M1, M2).”; [0146]-[0150] “first sub-pixel array (AA1) is driven at a frame frequency of 60 Hz and the second sub-pixel array (AA2) is driven at a frame frequency of 30 Hz” – note first sub-pixel array AA1 and second sub-pixel array AA2, each containing full color sub-pixels (SP1, SP2) – each of the arrays (AA1, AA2) provide sub-pixels of the same color).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply the alternating drive technique of Kwon to the redundant sub-pixel architecture of Ahmed. A person having ordinary skill in the art would have been motivated to use Kwon’s known frame-skipping and enable-signal scheme (EN1/EN2) to alternately activate Ahmed’s main and redundant sub-pixels of matching colors in successive frame intervals, yielding predictable advantages in power efficiency, uniformity, and lifetime performance. Further rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods and the combination yields nothing more than predictable results to one of ordinary skill in the art.
Kwon does not directly teach wherein the first-first sub-pixel and the first-second sub-pixel are connected to different data lines, the second-first sub-pixel and the second-second sub-pixel are commonly connected to one data line, and the third-first sub-pixel and the third-second sub-pixel are commonly connected to one data line.
Kim teaches a display device structure in which adjacent subpixels share data lines and wherein different subpixels within a unit pixel may be connected to different data lines (see at least [0008] “adjacent subpixels share data lines”; [0010] “Each of the unit pixels includes a plurality of subpixels which are connected to a first data line and a second data line. The first and second data lines are connected to the plurality of subpixels which are comprised in the unit pixel and are the same or different”; [0013] “The first subpixel and a second subpixel of the first unit pixel are connected to the first data line, and the third subpixel is connected to the second data line”; [0039] “the first one data line DL11 to DL1m can be connected to two or more subpixels sP.”; [0040] “the second one data line DL21 to DL2m can be connected to two or more subpixels sP.”; [0061]-[0064]: at least two subpixels of a unit pixel share a first data line while another subpixel is connected to a different data line and selected subpixels in adjacent unit pixels share a common data line). Kim therefore teaches or at least suggests a mixed data-line connection topology in which some corresponding subpixels share a common data line while other corresponding subpixels are connected to a different data line.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the mixed data-line connection topology of Kim into the display architecture resulting from the combination of Ahmed and Kwon. The combination would have yielded predictable results because the references each address compatible aspects of display panel design—Ahmed providing redundant sub-pixel structures, Kwon providing alternating frame driving of corresponding sub-pixel groups, and Kim providing established data-line connection schemes for sub-pixels within a unit pixel. A person having ordinary skill in the art would therefore have been motivated to adopt Kim’s known sub-pixel data-line configuration in the Ahmed/Kwon display device in order to achieve efficient wiring and driver utilization while implementing the alternating sub-pixel driving architecture.
As to claim 2, the combination of Ahmed, Kwon and Kim teach the display device of claim 1 (see above rejection), wherein the first-first, second-first, and third-first sub-pixels, and the first-second, second-second, and third-second sub-pixels are connected to a plurality of different gate lines among the plurality of gate lines, and wherein the plurality of different gate lines include a first gate line configured to receive a first scan signal, a second gate line configured to receive a second scan signal, and a third gate line configured to receive a light emission signal (see Kwon at least [0048] “The gate lines (GL1, GL2) can be divided into scan lines to which scan signals are applied and EM lines to which EM signals are applied.” and figs. 1, 3, 11, 20, 30-31: shared and divided scan lines (161–163, 171A/B–173A/B) between first and second sub-pixel arrays, scan signals (SCAN1–SCAN3)).
As to claim 3, the combination of Ahmed, Kwon and Kim teach the display device of claim 2 (see above rejection), wherein, during an (n)th frame period, a data voltage of an (n)th frame is applied to the first-first, second-first, and third-first sub-pixels, and pulses of the first and second scan signals and the light emission signal are applied to the first-first, second-first, and third-first sub-pixels, wherein, during an (n+1)th frame period after the (n)th frame period, the pulses of the first and second scan signals and the light emission signal are applied to the first-second, second-second, and third-second sub-pixels while a data voltage of an (n+1)th frame is applied to the first-second, second-second, and third-second sub-pixels, and wherein n is a positive integer (see Kwon at least [0048] “The gate lines (GL1, GL2) can be divided into scan lines to which scan signals are applied and EM lines to which EM signals are applied.” and figs. 1, 3, 11, 20, 25A-B: AA1 - drive at F1, F3; AA2 - drive at F2, F4 – note frame skip periods and vertical blank (VB) timing sequences indicate alternating frame-period operation, 30-31: shared and divided scan lines (161–163, 171A/B–173A/B) between first and second sub-pixel arrays, scan signals (SCAN1–SCAN3)).
As to claim 4, the combination of Ahmed, Kwon and Kim teach the display device of claim 2 (see above rejection), wherein during an (n)th frame period, a data voltage of an (n)th frame is applied to the first-first, second-first, and third-first sub-pixels, and pulses of the first and second scan signals and the light emission signal are applied to the first-first, second-first, and third-first sub-pixels, wherein, during an (n+1)th frame period after the (n)th frame period, none of the pulses of the first and second scan signals and the light emission signal are applied to first-first, second-first, third-first, first-second, second-second, and third-second sub-pixels, wherein, during an (n+2)th frame period after the (n+1)th frame period, a data voltage of an (n+2)th frame is applied to the first-second, second-second, and third-second sub-pixels, and the pulses of the first and second scan signals and the light emission signal are applied to the first-second, second-second, and third-second sub-pixels, and wherein n is a positive integer (see Kwon at least [0048] “The gate lines (GL1, GL2) can be divided into scan lines to which scan signals are applied and EM lines to which EM signals are applied.” and figs. 1, 3, 11, 20, 25A-B: AA1 - drive at F1, F3; AA2 - drive at F2, F4 – note frame skip periods and vertical blank (VB) timing sequences indicate alternating frame-period operation, 30-31: shared and divided scan lines (161–163, 171A/B–173A/B) between first and second sub-pixel arrays, scan signals (SCAN1–SCAN3)).
As to claim 5, the combination of Ahmed, Kwon and Kim teach the display device of claim 2 (see above rejection), wherein during an (n)th frame period, pulses of the first and second scan signals are applied to the first-first, second-first, and third-first sub-pixels, and a pulse of the light emission signal is applied to the first-second, second-second and third-second sub-pixels, wherein, during an (n+1)th frame period after the (n)th frame period, the pulse of the light emission signal is applied to the first-second, second-second, and third-second sub-pixels, and the pulses of the first and second scan signals are applied to the first-second, second-second and third-second sub-pixels, and wherein n is a positive integer (see Kwon at least [0048] “The gate lines (GL1, GL2) can be divided into scan lines to which scan signals are applied and EM lines to which EM signals are applied.” and figs. 1, 3, 11, 20, 25A-B: AA1 - drive at F1, F3; AA2 - drive at F2, F4 – note frame skip periods and vertical blank (VB) timing sequences indicate alternating frame-period operation, 30-31: shared and divided scan lines (161–163, 171A/B–173A/B) between first and second sub-pixel arrays, scan signals (SCAN1–SCAN3)).
As to claim 6, the combination of Ahmed, Kwon and Kim teach the display device of claim 2 (see above rejection), wherein during an (n)th frame period, a data voltage of an (n)th frame is applied to the first-first, second-first, and third-first sub-pixels, and the first and second scan signals are applied to the first-first, second-first, and third-first sub-pixels, wherein during an (n+1)th frame period after the (n)th frame period, a pulse of the light emission signal is applied to the first-second, second-second, and third-second sub-pixels, wherein during an (n+2)th frame period after the (n+1)th frame period, a data voltage of an (n+2)th frame is applied to the first-second, second-second, and third-second sub-pixels, and pulses of the first and second scan signals are applied to the first-second, second-second, and third-second sub-pixels, and wherein during an (n+3)th frame period after the (n+2)th frame period, the pulse of the light emission signal is applied to the first-second, second-second, and third-second sub-pixels, and wherein n is a positive integer (see Kwon at least [0048] “The gate lines (GL1, GL2) can be divided into scan lines to which scan signals are applied and EM lines to which EM signals are applied.” and figs. 1, 3, 11, 20, 25A-B: AA1 - drive at F1, F3; AA2 - drive at F2, F4 – note frame skip periods and vertical blank (VB) timing sequences indicate alternating frame-period operation, 30-31: shared and divided scan lines (161–163, 171A/B–173A/B) between first and second sub-pixel arrays, scan signals (SCAN1–SCAN3)).
As to claim 7, the combination of Ahmed, Kwon and Kim teach the display device of claim 2 (see above rejection), wherein the first-first and first-second sub-pixels are respectively connected to first-first and first-second gate lines branched from the first gate line and configured to receive a first scan signal, wherein the second-first and second-second sub-pixels are respectively connected to the second-first and second-second gate lines branched from the second gate line and configured to receive a second scan signal, and wherein the third-first and third-second sub-pixels are respectively connected to the third-first and third-second gate lines branched from the third gate line and configured to receive a light emission signal (see Kwon at least [0048] “The gate lines (GL1, GL2) can be divided into scan lines to which scan signals are applied and EM lines to which EM signals are applied.” and figs. 1, 3, 11, 20-23, 25A-B: AA1 - drive at F1, F3; AA2 - drive at F2, F4 – note frame skip periods and vertical blank (VB) timing sequences indicate alternating frame-period operation, 30-31: scan lines 171A/B–173A/B branched from shared scan lines 161–163).
As to claim 8, the combination of Ahmed, Kwon and Kim teach the display device of claim 7 (see above rejection), further comprising: a first-first selection switch element connected between the first gate line and first-first gate line, a second-first selection switch element connected between the second gate line and second-first gate line, and a third-first selection switch element connected between the third gate line and the third-first gate line, and the first-first, second-first and third-first selection switch elements being configured to turn on in response to a first mask signal; and a first-second selection switch element connected between the first gate line and the first-second gate line, a second-second selection switch element connected between the second gate line and the second-second gate line, and a third-second selection switch element connected between the third gate line and the third-second gate line, and the first-second, second-second and third-second selection switch elements being configured to turn on in response to a second mask signal, and wherein the first and second mask signals are applied from a timing controller (see Kwon at least figs. 21-23: demultiplexers (113, 114) use switch elements M1–M2 controlled by MUX selection signals MUX1/MUX2 generated by the timing controller 130, data line reset units 141/142 include switch elements M3/M4 controlled by enable signals EN1/EN2 (on/off per frame skip), MUX1/MUX2 ≈ mask/selection signals alternating each frame; figs. 30 – 31: scan lines 171A/B–173A/B branched from shared scan lines 161–163 correspond to first/second sub-pixel arrays, each selectively activated via control lines (EN1, EN2 ≈ mask signals)).
As to claim 9, the combination of Ahmed, Kwon and Kim teach the display device of claim 8 (see above rejection), wherein, during an (n)th frame period, a data voltage of an (n)th frame is applied to the first-first, second-first, third-first sub-pixels and the first-second, second-second and third-second sub-pixels, pulses of the first and second scan signals and the light emission signals are applied to the first-first, second-first, third-first sub-pixels and the first-second, second-second and third-second sub-pixels, and the first mask signal of a first voltage level is applied to the first-first, second-first and third-first selection switch elements and the second mask signal of a second voltage level is applied to the first-second, second-second and third-second selection switch elements, wherein, during an (n+1)th frame period after the (n)th frame period, a data voltage of an (n+1)th frame is applied to the first-first, second-first, third-first sub-pixels and the first-second, second-second and third-second sub-pixels, the pulses of the first and second scan signals and the light emission signal are applied to the first-first, second-first, third-first sub-pixels and the first-second, second-second and third-second sub-pixels, and the first mask signal of the second voltage level is applied to the first-first, second-first and third-first selection switch elements and the second mask signal of the first voltage level is applied to the first-second, second-second and third-second selection switch elements, wherein n is a positive integer, and wherein the first voltage level is lower than the second voltage level (see Kwon at least figs. 21-23, 25, 30-31: demultiplexers (113, 114) use switch elements M1–M2 controlled by MUX selection signals MUX1/MUX2 generated by the timing controller 130, data line reset units 141/142 include switch elements M3/M4 controlled by enable signals EN1/EN2 (on/off per frame skip), MUX1/MUX2 ≈ mask/selection signals alternating each frame; gate-on (VGL) / gate-off (VGH) voltage levels to alternately enable or disable reset units and demultiplexers per frame period, correspond to the “first/second voltage levels” in the mask-signal).
As to claim 10, the combination of Ahmed, Kwon and Kim teach the display device of claim 8 (see above rejection), wherein during an (n)th frame period, a data voltage of an (n)th frame is applied to the first-first, second-first, third-first sub-pixels and the first-second, second-second and third-second sub-pixels, pulses of the first and second scan signals and the light emission signal are applied to the first-first, second-first, third-first sub-pixels and the first-second, second-second and third-second sub-pixels, and the first mask signal of a first voltage level is applied to the first-first, second-first and third-first selection switch elements and the second mask signal of a second voltage level is applied to the first-second, second-second and third-second selection switch elements, wherein, during an (n+1)th frame period after the (n)th frame period, pulses of the first and second scan signals and the light emission signal are applied to the first-first, second-first, and third-first sub-pixels and the first-second, second-second and third-second sub-pixels, and the first mask signal of the second voltage level is applied to the first-first, second-first and third-first selection switch elements and the second mask signal of the second voltage level is applied to the first-second, second-second and third-second selection switch elements, wherein, during an (n+2)th frame period after the (n+1)th frame period, a data voltage of an (n+2)th frame is applied to the first-first, second-first, and third-first sub-pixels and the first-second, second-second and third-second sub-pixels, the pulses of the first and second scan signals and the light emission signal are applied to the first-first, second-first, third-first sub-pixels and the first-second, second-second and third-second sub-pixels, and the first mask signal of the second voltage level is applied to the first-first, second-first and third-first selection switch elements and the second mask signal of the first voltage level is applied to the first-second, second-second and third-second selection switch elements, wherein, during an (n+3)th frame period after the (n+2)th frame period, pulses of the first and second scan signals and the light emission signal are applied to the first-first, second-first, and third-first sub-pixels and the first-second, second-second and third-second sub-pixels, and the first mask signal of the second voltage is applied to the first-first, second-first and third-first selection switch elements and the second mask signal of the second voltage level is applied to the first-second, second-second and third-second selection switch elements, wherein n is a positive integer, and wherein the first voltage level is lower than the second voltage level (see Kwon at least figs. 21-23, 25, 30-31: demultiplexers (113, 114) use switch elements M1–M2 controlled by MUX selection signals MUX1/MUX2 generated by the timing controller 130, data line reset units 141/142 include switch elements M3/M4 controlled by enable signals EN1/EN2 (on/off per frame skip), MUX1/MUX2 ≈ mask/selection signals alternating each frame; gate-on (VGL) / gate-off (VGH) voltage levels to alternately enable or disable reset units and demultiplexers per frame period, correspond to the “first/second voltage levels” in the mask-signal).
As to claim 22, the combination of Ahmed, Kwon and Kim teach the display device of claim 21 (see above rejection), wherein the controller is further configured to: in response to determining that pixel data of an input image corresponds to a moving image, alternatingly drive the main group of sub-pixels and the redundancy group of sub-pixels to display the pixel data at a first driving frequency, and in response to determining that the pixel data of the input image corresponds to a still image to be displayed for multiple frames, alternatingly drive the main group of sub-pixels and the redundancy group of sub-pixels to display the pixel data at a second driving frequency lower than the first driving frequency (see Kwon at least figs. 8 and 10; [0080] “the timing controller (130) detects the frame frequency of image data input from the host system (200) (S1). The image data may include first image data to be displayed on the first sub-pixel array (AA1) and second image data to be displayed on the second sub-pixel array (AA1). The first and second image data may have the same or different frame frequencies.”; [0081] “the frame frequency may be changed by the timing controller (130) depending on the movement of the first image data and the second image data. For example, the timing controller (130) can improve power consumption without degrading image quality by lowering the frame frequency of image data with less movement among the first and second image data.”; [0092] “Referring to FIG. 10, the first image data can be displayed on the first sub-pixel array (AA1) at a frame frequency of 60 Hz at the resolution of the first sub-pixel array (AA1).The second image data can be displayed on the second sub-pixel array (AA2) at a frame frequency of 30 Hz at the resolution of the second sub-pixel array (AA2). The first video data may be a video of a content or application with a lot of movement. The second video data may be a video of the standby screen, or a video of content or application with little movement.”; figs. 20-30: EN1 and EN2 signals drive the sub-pixel arrays AA1 SP1 and AA2 SP2 in alternating frames (F1/F3 vs F2/F4) and [0135] “the first demultiplexer (113) can alternately supply data voltages output from the output channels of the first data driving unit (111) to a plurality of data lines (61) during the active section (AT) of the driving frame period .. The second demultiplexer (114) can alternately supply data voltages output from the output channels of the second data driving unit (112) to a plurality of data lines (62) during the active section (AT) of the driving frame period”; [0144] “The MUX selection signals (MUX1, MUX) for controlling the demultiplexers (141, 142) are generated in reverse phase during the active section [ACT (Normal)] of the driving frame period, so as to alternately turn on the switch elements (M1, M2).”; [0146]-[0150] “first sub-pixel array (AA1) is driven at a frame frequency of 60 Hz and the second sub-pixel array (AA2) is driven at a frame frequency of 30 Hz” – note first sub-pixel array AA1 and second sub-pixel array AA2, each containing full color sub-pixels (SP1, SP2) - the two arrays (AA1, AA2) provide the “first” and “second” sub-pixels of the same color – see fig. 3 and “[0043] “each pixel (P) includes R, G, and B sub-pixels”).
As to claim 23, the combination of Ahmed, Kwon and Kim teach the display device of claim 21 (see above rejection), wherein the first-first, second-first, and third-first sub-pixels, and the first-second, second-second, and third-second sub-pixels are connected to a plurality of different gate lines among the plurality of gate lines, and wherein the plurality of different gate lines include a first gate line configured to receive a first scan signal, a second gate line configured to receive a second scan signal, and a third gate line configured to receive a light emission signal (see Kwon at least [0048] “The gate lines (GL1, GL2) can be divided into scan lines to which scan signals are applied and EM lines to which EM signals are applied.” and figs. 1, 3, 11, 20, 25A-B: AA1 - drive at F1, F3; AA2 - drive at F2, F4 – note frame skip periods and vertical blank (VB) timing sequences indicate alternating frame-period operation, 30-31: shared and divided scan lines (161–163, 171A/B–173A/B) between first and second sub-pixel arrays, scan signals (SCAN1–SCAN3)).
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (KR 2021-0144403 A) in view of Ahmed et al. (USPN 2020/0327843 A1), further in view of Kim et al. (USPN 2022/0208115 A1).
As to claim 11, Kwon teaches a display device comprising:
a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels (see at least fig. 1: display panel 100, data drivers 111/112, gate drivers 121/122, pixels P);
a data driver configured to output data voltages to the plurality of data lines (see at least fig. 1: data drivers 111, 112);
a gate driver configured to output gate signals to the plurality of gate lines (see at least fig. 1: gate drivers 121 and 122); and
a timing controller (see at least fig. 1: timing controller 130) configured to:
in response to determining that pixel data of an input image corresponds to a moving image, supply a gate timing control signal to the gate driver at a first driving frequency, and in response to determining that the pixel data of the input image corresponds to a still image to be displayed for multiple frames, supply the gate timing control signal to the gate driver at a second driving frequency lower than the first driving frequency (see at least figs. 8 and 10; [0080] “the timing controller (130) detects the frame frequency of image data input from the host system (200) (S1). The image data may include first image data to be displayed on the first sub-pixel array (AA1) and second image data to be displayed on the second sub-pixel array (AA1). The first and second image data may have the same or different frame frequencies.”; [0081] “the frame frequency may be changed by the timing controller (130) depending on the movement of the first image data and the second image data. For example, the timing controller (130) can improve power consumption without degrading image quality by lowering the frame frequency of image data with less movement among the first and second image data.”; [0092] “Referring to FIG. 10, the first image data can be displayed on the first sub-pixel array (AA1) at a frame frequency of 60 Hz at the resolution of the first sub-pixel array (AA1).The second image data can be displayed on the second sub-pixel array (AA2) at a frame frequency of 30 Hz at the resolution of the second sub-pixel array (AA2). The first video data may be a video of a content or application with a lot of movement. The second video data may be a video of the standby screen, or a video of content or application with little movement.”).
Kwon does not directly teach wherein each of the plurality of pixels includes: a first-first sub-pixel configured to emit a first color of light and a first-second sub-pixel configured to emit the first color of light; a second-first sub-pixel configured to emit a second color of light and a second-second sub-pixel configured to emit the second color of light; and a third-first sub-pixel configured to emit a third color of light and a third-second sub-pixel configured to emit the third color of light.
Ahmed teaches wherein each of the plurality of pixels includes: a first-first sub-pixel configured to emit a first color of light and a first-second sub-pixel configured to emit the first color of light; a second-first sub-pixel configured to emit a second color of light and a second-second sub-pixel configured to emit the second color of light; and a third-first sub-pixel configured to emit a third color of light and a third-second sub-pixel configured to emit the third color of light (see at least figs. 7A-B and [0041] “drive rows (e.g., 730a-c) of pixels in the display as well as the individual sub-pixel elements (e.g., red, green, and blue) of the array of pixels to cause corresponding graphics to be displayed. Further, redundant sets of sub-pixels may be provided to implement each pixel (e.g., 705) in the display. In this example, three redundant sets of red, green, and blue LED elements may be provided to redundantly implement each pixel (e.g., 705)”).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the redundant sub-pixel architecture of Ahmed into the display device of Kwon. A person having ordinary skill in the art would have recognized that implementing Ahmed’s redundant sub-pixel structure within Kwon’s display system would allow the timing controller and driving circuitry of Kwon to selectively drive corresponding sub-pixels or sub-pixel groups while benefiting from the redundancy advantages taught by Ahmed. The combination therefore represents the predictable use of known pixel structures (Ahmed) within a known display driving architecture (Kwon) to achieve recognized benefits including improved reliability, lifetime, and display uniformity. Further rationale supporting the conclusion of obviousness is that the claimed elements were known in the prior art and could be combined by known methods to yield predictable results to one of ordinary skill in the art.
Kwon and Ahmed do not directly teach wherein the first-first sub-pixel and the first-second sub-pixel are connected to different data lines, the second-first sub-pixel and the second-second sub-pixel are commonly connected to one data line, and the third-first sub-pixel and the third-second sub-pixel are commonly connected to one data line.
Kim teaches wherein the first-first sub-pixel and the first-second sub-pixel are connected to different data lines, the second-first sub-pixel and the second-second sub-pixel are commonly connected to one data line, and the third-first sub-pixel and the third-second sub-pixel are commonly connected to one data line (see at least [0008] “adjacent subpixels share data lines”; [0010] “Each of the unit pixels includes a plurality of subpixels which are connected to a first data line and a second data line. The first and second data lines are connected to the plurality of subpixels which are comprised in the unit pixel and are the same or different”; [0013] “The first subpixel and a second subpixel of the first unit pixel are connected to the first data line, and the third subpixel is connected to the second data line”; [0039] “the first one data line DL11 to DL1m can be connected to two or more subpixels sP.”; [0040] “the second one data line DL21 to DL2m can be connected to two or more subpixels sP.”; [0061]-[0064]: at least two subpixels of a unit pixel share a first data line while another subpixel is connected to a different data line and selected subpixels in adjacent unit pixels share a common data line). Kim therefore teaches or at least suggests a mixed data-line connection topology in which some corresponding subpixels share a common data line while other corresponding subpixels are connected to a different data line.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the mixed data-line connection topology of Kim into the display architecture resulting from the combination of Kwon and Ahmed. The combination would have yielded predictable results because the references each address compatible aspects of display panel design—Ahmed providing redundant sub-pixel structures, Kwon providing alternating frame driving of corresponding sub-pixel groups, and Kim providing established data-line connection schemes for sub-pixels within a unit pixel. A person having ordinary skill in the art would therefore have been motivated to adopt Kim’s known sub-pixel data-line configuration in the Kwon/Ahmed display device in order to achieve efficient wiring and driver utilization while implementing the alternating sub-pixel driving architecture.
As to claim 12, the combination of Kwon, Ahmed and Kim teach the display device of claim 11 (see above rejection), wherein the first-first, second-first, and third-first sub-pixels and the first-second, second-second, and third-second sub-pixels are connected to a plurality of different gate lines among the plurality of gate lines (see at least figs. 1 and 3 and [0043] “each pixel (P) includes R, G, and B sub-pixels as illustrated in FIG. 3.”; [0047] “Gate drivers (121, 122) are arranged on each of the left and right bezels of the display panel (100) and can supply gate signals to the gate lines (GL1, GL2) in a double feeding manner.”; [0048] “The gate lines (GL1, GL2) can be divided into scan lines to which scan signals are applied and EM lines to which EM signals are applied.”).
As to claim 13, the combination of Kwon, Ahmed and Kim teach the display device of claim 12 (see above rejection), wherein the timing controller is further configured to: output a data voltage of an (n)th frame for the first-first, second-first, and third-first sub-pixels, and output a pulse of the gate timing control signal during an (n)th frame period, and output a data voltage of an (n+1)th frame for the first-second, second-second, and third-second sub-pixels, and output the pulse of the gate timing control signal during an (n+1)th frame period after the (n)th frame period, and wherein n is a positive integer (see Kwon at least [0048] “The gate lines (GL1, GL2) can be divided into scan lines to which scan signals are applied and EM lines to which EM signals are applied.” and figs. 1, 3, 11, 20-23, 25A-B: AA1 - drive at F1, F3; AA2 - drive at F2, F4 – note frame skip periods and vertical blank (VB) timing sequences indicate alternating frame-period operation, 30-31: shared and divided scan lines (161–163, 171A/B–173A/B) between first and second sub-pixel arrays, scan signals (SCAN1–SCAN3)).
As to claim 14, the combination of Kwon, Ahmed and Kim teach the display device of claim 12 (see above rejection), wherein the timing controller is further configured to: output a data voltage of an (n)th frame for the first-first, second-first, and third-first sub-pixels, and a pulse of the gate timing control signal, during an (n)th frame period, not output a data voltage and the pulse of the gate timing control signal, during an (n+1)th frame period after the (n)th frame period, and output a data voltage of an (n+2) frame for the first-second, second-second, and third-second sub-pixels, and the pulse of the gate timing control signal, during the (n+2)th frame period after the (n+1)th frame period, and wherein n is a positive integer (see Kwon at least [0048] “The gate lines (GL1, GL2) can be divided into scan lines to which scan signals are applied and EM lines to which EM signals are applied.” and figs. 1, 3, 11, 20-23, 25A-B: AA1 - drive at F1, F3; AA2 - drive at F2, F4 – note frame skip periods and vertical blank (VB) timing sequences indicate alternating frame-period operation, 30-31: shared and divided scan lines (161–163, 171A/B–173A/B) between first and second sub-pixel arrays, scan signals (SCAN1–SCAN3)).
As to claim 15, the combination of Kwon, Ahmed and Kim teach the display device of claim 12 (see above rejection), wherein the gate timing control signal includes a first gate timing control signal for generating a first scan signal, a second gate timing control signal for generating a second scan signal, and a third gate timing control signal for generating a light emission signal, wherein the timing controller is further configured to: output pulses of the first and second gate timing control signals for the first-first, second-first, and third-first sub-pixels, and a pulse of the third gate timing control signal for the first-second, second-second and third-second sub-pixels, during an (n)th frame period, and output the pulse of the third gate timing control signal for the first-second, second-second, and third-second sub-pixels, and the pulses of the first and second gate timing control signals for the first-second, second-second and third-second sub-pixels, during an (n+1)th frame period after the (n)th frame period, and wherein n is a positive integer. (see Kwon at least [0048] “The gate lines (GL1, GL2) can be divided into scan lines to which scan signals are applied and EM lines to which EM signals are applied.” and figs. 1, 3, 11, 20-23, 25A-B: AA1 - drive at F1, F3; AA2 - drive at F2, F4 – note frame skip periods and vertical blank (VB) timing sequences indicate alternating frame-period operation, 30-31: shared and divided scan lines (161–163, 171A/B–173A/B) between first and second sub-pixel arrays, scan signals (SCAN1–SCAN3)).
As to claim 16, the combination of Kwon, Ahmed and Kim teach the display device of claim 12 (see above rejection), wherein the gate timing control signal includes a first gate timing control signal for generating a first scan signal, a second gate timing control signal for generating a second scan signal, and a third gate timing control signal for generating a light emission signal, wherein the timing controller is further configured to: output a data voltage of an (n)th frame for the first-first, second-first, and third-first sub-pixels, and pulses of the first and second gate timing control signals, during an (n)th frame period, output a pulse of the third gate timing control signal for the first-second, second-second, and third-second sub-pixels, during an (n+1)th frame period after the (n)th frame period, output a data voltage of an (n+2)th frame for the first-second, second-second, and third-second sub-pixels, and the pulses of the first and second gate timing control signals, during an (n+2)th frame period after the (n+1)th frame period, and output the pulse of the third gate timing control signal for the first-second, second-second, and third-second sub-pixels, during an (n+3)th frame period after the (n+2)th frame period, and wherein n is a positive integer (see Kwon at least [0048] “The gate lines (GL1, GL2) can be divided into scan lines to which scan signals are applied and EM lines to which EM signals are applied.” and figs. 1, 3, 11, 20-23, 25A-B: AA1 - drive at F1, F3; AA2 - drive at F2, F4 – note frame skip periods and vertical blank (VB) timing sequences indicate alternating frame-period operation, 30-31: shared and divided scan lines (161–163, 171A/B–173A/B) between first and second sub-pixel arrays, scan signals (SCAN1–SCAN3)).
As to claim 17, the combination of Kwon, Ahmed and Kim teach the display device of claim 12 (see above rejection), wherein the first-first and first-second sub-pixels are respectively connected to first-first and first-second gate lines branched from a first gate line configured to receive a first scan signal, wherein the second-first and second-second sub-pixels are respectively connected to second-first and second-second gate lines branched from a second gate line configured to receive a second scan signal, and wherein the third-first and third-second sub-pixels are respectively connected to third-first and third-second gate lines branched from a third gate line configured to receive a light emission signal (see Kwon at least [0048] “The gate lines (GL1, GL2) can be divided into scan lines to which scan signals are applied and EM lines to which EM signals are applied.” and figs. 1, 3, 11, 20-23, 25A-B: AA1 - drive at F1, F3; AA2 - drive at F2, F4 – note frame skip periods and vertical blank (VB) timing sequences indicate alternating frame-period operation, 30-31: scan lines 171A/B–173A/B branched from shared scan lines 161–163).
As to claim 18, the combination of Kwon, Ahmed and Kim teach the display device of claim 17 (see above rejection), further comprising: a first-first selection switch element connected between the first gate line and first-first gate line, a second-first selection switch element connected between the second gate line and second-first gate line, and a third-first selection switch element connected between the third gate line and the third-first gate line, and the first-first, second-first and third-first selection switch elements being configured to turn on in response to a first mask signal; and a first-second selection switch element connected between the first gate line and the first-second gate line, a second-second selection switch element connected between the second gate line and the second-second gate line, and a third-second selection switch element connected between the third gate line and the third-second gate line, and the first-second, second-second and third-second selection switch elements being configured to turn on in response to a second mask signal, and wherein the first and second mask signals are applied from a timing controller (see Kwon at least figs. 21-23: demultiplexers (113, 114) use switch elements M1–M2 controlled by MUX selection signals MUX1/MUX2 generated by the timing controller 130, data line reset units 141/142 include switch elements M3/M4 controlled by enable signals EN1/EN2 (on/off per frame skip), MUX1/MUX2 ≈ mask/selection signals alternating each frame; figs. 30 – 31: scan lines 171A/B–173A/B branched from shared scan lines 161–163 correspond to first/second sub-pixel arrays, each selectively activated via control lines (EN1, EN2 ≈ mask signals)).
As to claim 19, the combination of Kwon, Ahmed and Kim teach the display device of claim 18 (see above rejection), wherein the gate timing control signal includes a first gate timing control signal for generating the first scan signal, a second gate timing control signal for generating the second scan signal, and a third gate timing control signal for generating the light emission signal, and wherein the timing controller is further configured to: output data voltages of an (n)th frame for the first-first, second-first, and third-first sub-pixels and the first-second, second-second, and third-second sub-pixels, pulses of the first to third gate timing control signals, and the first mask signal of a first voltage level and the second mask signal of a second voltage level, during an (n)th frame period, and output data voltages of an (n+1)th frame for the first-first, second-first, and third-first sub-pixels and the first-second, second-second, and third-second sub-pixels, the pulses of the first to third gate timing control signals, and the first mask signal of the second voltage level and the second mask signal of the first voltage level, during an (n+1)th frame period after the (n)th frame period, wherein n is a positive integer, and wherein the first voltage level is lower than the second voltage level (see Kwon at least figs. 21-23, 25, 30-31: demultiplexers (113, 114) use switch elements M1–M2 controlled by MUX selection signals MUX1/MUX2 generated by the timing controller 130, data line reset units 141/142 include switch elements M3/M4 controlled by enable signals EN1/EN2 (on/off per frame skip), MUX1/MUX2 ≈ mask/selection signals alternating each frame; gate-on (VGL) / gate-off (VGH) voltage levels to alternately enable or disable reset units and demultiplexers per frame period, correspond to the “first/second voltage levels” in the mask-signal).
As to claim 20, the combination of Kwon, Ahmed and Kim teach the display device of claim 18 (see above rejection), wherein the gate timing control signal includes a first gate timing control signal for generating the first scan signal, a second gate timing control signal for generating the second scan signal, and a third gate timing control signal for generating the light emission signal, and wherein the timing controller is further configured to: output data voltages of an (n)th frame for the first-first, second-first, and third-first sub-pixels and the first-second, second-second, and third-second sub-pixels, pulses of the first to third gate timing control signals, and the first mask signal of a first voltage level and the second mask signal of a second voltage level, during an (n)th frame period, output pulses of the first to third gate timing control signals for the first-first, second-first, and third-first sub-pixels and the first-second, second-second and third-second sub-pixels, and the first and second mask signals of the second voltage level, during an (n+1)th frame period after the (n)th frame period, output a data voltage of an (n+2)th frame for the first-first, second-first, and third-first sub-pixels and the first-second, second-second, and third-second sub-pixels, the pulses of the first to third gate timing control signals, and the first mask signal of the second voltage level and the second mask signal of the first voltage level, during an (n+2) frame period after the (n+1)th frame period, output pulses of the first to third gate timing control signals for the first-first, second-first, and third-first sub-pixels and the first-second, second-second and third-second sub-pixels, and the first and second mask signals of the second voltage level, during an (n+3)th frame period after the (n+2)th frame period, wherein n is a positive integer, and wherein the first voltage level is set lower than the second voltage level (see Kwon at least figs. 21-23, 25, 30-31: demultiplexers (113, 114) use switch elements M1–M2 controlled by MUX selection signals MUX1/MUX2 generated by the timing controller 130, data line reset units 141/142 include switch elements M3/M4 controlled by enable signals EN1/EN2 (on/off per frame skip), MUX1/MUX2 ≈ mask/selection signals alternating each frame; gate-on (VGL) / gate-off (VGH) voltage levels to alternately enable or disable reset units and demultiplexers per frame period, correspond to the “first/second voltage levels” in the mask-signal).
Response to Arguments
Applicant’s arguments filed 2/3/2026 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER L ZUBAJLO whose telephone number is (571)270-1551. The examiner can normally be reached Monday - Thursday 10 am - 8 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KE XIAO can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JENNIFER L ZUBAJLO/Examiner, Art Unit 2627 3/16/2026
/KE XIAO/Supervisory Patent Examiner, Art Unit 2627