Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in KR on 16 February 2024. It is noted, however, that applicant has not filed a certified copy of the KR10-2024-0022482 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 17, and 20-21 is/are rejected under 35 U.S.C. 102(a)(2) as being unpatentable by Li (US 2025.0131879).
Regarding claim 1, Li disclose:
A gate driving circuit, comprising: a first pulse output part configured to output a first pulse of a scan signal through an output node, and a second pulse output part configured to output a second pulse of the scan signal through the output node (see Fig. 2-6; gate driving circuit GAO1 to output a first scan pulse OUT1 at t2 and a second scan pulse OUT1 after t4, through output node OUT1)
wherein the first pulse output part includes: a first output transistor having a gate electrode connected to a first control node; and a second output transistor having a gate electrode connected to a second control node (see Fig. 2-6; first pulse part has first output TFT T8 at first control node N7 and second output control node N6)
wherein the second pulse output part includes: a third control node; and a third output transistor connected to the third control node, and wherein the second pulse output part is connected to the second control node and the output node of the first pulse output part (see Fig. 2-6; second pulse output part has third control node N7, third output TFT T8, where T8 is connected to N7 and connected to N6 via T9 and output node OUT1).
Regarding claim 2, the rejection of claim 1 is incorporated herein. Li disclose:
the output node is configured to: simultaneously output the first pulse of the scan signal and a first carry signal, and then output the second pulse of the scan signal simultaneously while a second carry signal is output through a second carry signal node (see Fig. 2-6; where first and second carry signals are output from OUT1 to IN1 simultaneously with output first and second pulses OUT1).
Regarding claim 17, Li disclose:
A display device comprising: a display panel including a plurality of data lines, a plurality of gate lines, and at least one sub-pixel (see Fig. 1, 3; data line Da, gate line G, pixel PX)
a data driver connected to the plurality of data lines, and configured to output a data voltage to a data line among the plurality of data lines that is connected to the at least one sub-pixel (see Fig. 1, 3; [0041]; data driver (not shown to supply data voltages to Da among data lines connected to pixels PX)
a gate driver connected to the plurality of gate lines, and configured to: supply a first scan pulse and second scan pulse to a gate line among the plurality of gate lines that is connected to the at least one sub-pixel for causing the at least one sub-pixel to emit light based on the data voltage during a time period between the first scan pulse and the second scan pulse (see Fig. 1, 3-6; gate driver GOA1 to supply first scan pulse OUT1 t2/t3 and second scan pulse OUT1 after t4, where light emission period t4 occurs between OUT1 (t2/t3) and second pulse OUT1 (after t4))
Regarding claim 20, the rejection of claim 17 is incorporated herein. Li further disclose
the gate driver includes a plurality of gate driving circuits and at least one of the plurality of gate driving circuits includes: a first pulse output part configured to output the first scan pulse through an output node, (see Fig. 2-6; first pulse output part to output a first scan pulse OUT1 at t2)
and a second pulse output part configured to output the second scan pulse through the output node (see Fig. 2-6; second pulse output part to output OUT1 after t4, through output node OUT1).
Regarding claim 21, the rejection of claim 20 is incorporated herein. Li further disclose
the first pulse output part includes: a first output transistor having a gate electrode connected to a first control node; and a second output transistor having a gate electrode connected to a second control node (see Fig. 2-6; first pulse part has first output TFT T8 at first control node N7 and second output control node N6)
wherein the second pulse output part includes: a third control node; and a third output transistor connected to the third control node, and wherein the second pulse output part is connected to the second control node and the output node of the first pulse output part (see Fig. 2-6; second pulse output part has third control node N7, third output TFT T8, where T8 is connected to N7 and connected to N6 via T9 and output node OUT1).
Allowable Subject Matter
Claims 9-16 are allowed. Particularly, claim 9’s recitation of “A display device comprising: a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits; a data driver configured to supply a pixel grayscale voltage and a black grayscale voltage to the plurality of data lines; and a gate driver configured to supply a scan signal to the plurality of gate lines, wherein the gate driver includes a plurality of signal transmission parts connected to a plurality of clock wires, wherein an n-th signal transmission part among the plurality of signal transmission parts includes: a first pulse output part configured to output a first pulse of the scan signal; and a second pulse output part configured to output a second pulse of the scan signal, wherein n is a natural number, wherein each of the plurality of pixel circuits includes: a driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode configured to receive a ground voltage; a light-emitting element configured to emit light, the light-emitting element including an anode electrode configured to a pixel driving voltage, and a cathode electrode connected to the second node; a first switching transistor connected between a data line among the plurality of data lines and the first node, and configured to be turned on in response to each of the first pulse of the scan signal and the second pulse of the scan signal; a second switching transistor connected between a power line configured to receive a reference voltage and the second node, and configured to be turned on in response to each of the first pulse of the scan signal and the second pulse of the scan signal; and a capacitor connected between the first node and the second node, and wherein the first node is configured to receive the pixel grayscale voltage through the data line when the first pulse of the scan signal is input to the gate electrodes of the first and second switching transistors, and then receive the black grayscale voltage when the second pulse of the scan signal is input to the gate electrodes of the first and second switching transistors “, in combination with other elements of the claims, cannot be found alone or in combination within the cited prior art, particularly in the closest cited art Li (US 2025.0131879). Claims 10-16 being allowable by dependency.
Claims 3-8 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH BUKOWSKI whose telephone number is (571)270-7913. The examiner can normally be reached Monday - Friday // 0730-1530.
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/kenneth bukowski/ Primary Examiner, Art Unit 2621