DETAILED ACTION
Claims 1-20 are presented for examination.
The present application is being examined under the AIA (America Invents Act) First Inventor to File.
This Office Action is Non-Final.
Claims 1, 7 and 14 are independent claims. Claims 2-6, 8-13, 15-21 are dependent claims.
This action is responsive to the following communication: corresponding claims filed on 12-12-2024.
Domestic Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12-12-2024 in compliance with the provisions of 37 CFR 1.97
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1- 20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by U.S. Publication No. 2003/0197537 (hereinafter, “Saint-Laurent”).
As per claim(s) 1, 71, Saint-Laurent an apparatus comprising:
a clock generator circuit configured to generate a global clock signal; (master PLL to generate master clock; Fig. 6 )
a forward clock network configured to distribute the global clock signal to a plurality of distributed clock signals; (global clock to distribute from the master clock clock signals to devices 130A-130C; Fig 3)
a backward clock network configured to select at least one of the plurality of distributed clock signals to generate at least one back clock signal; and (feedback lines that can be used for phased adjustment of the master clock; ¶s [0037]-[0040], Fig 3)
a control circuit configured to perform a phase comparison between the global clock signal and the at least one back clock signal; and (¶[0032] discloses how the alignment control unit 230 may be used to control the VDE 220 to align the global clock signal (i.e., phase alignment) for clock skew compensation. This adjustment is performed by a detector that compares the frequency of the divided clock and the frequency of the local clock that has been fed back. ¶ [0045] )
wherein the clock generator circuit is further configured to modify the global clock signal using a result of the phase comparison. ( ¶ [0038] discloses how a local clock signal from the local clock region 150C may be returned to the master PLL 120 for master clock phase alignments, via feedback line 306 )
As per claim(s) 2, 12, Saint-Laurent discloses an apparatus wherein to modify the global clock signal, the clock generator circuit is further configured to decrease a frequency of the global clock signal using the result of the phase comparison. (¶[0059] discloses how the respective clock processor nodes 130A-130N is to be increased or decreased)
As per claim 3, Saint-Laurent discloses an apparatus wherein to modify the global clock signal, the clock generator circuit is further configured to phase shift the global clock signal using the result of the phase comparison. ( ¶ [0032] discloses align the global clock signal (i.e., phase alignment) for clock skew compensation )
As per claim 6, Saint-Laurent discloses an apparatus wherein to generate the global clock signal, the clock generator circuit is further configured to generate a plurality of phasors, and (a master phase-locked loop (PLL) 120 to feed an array of PLLs; ¶
wherein to perform the phase comparison, the control circuit is further configured to perform respective phase comparisons of the at least one back clock signal and the plurality of phasors. (align the global clock signal (i.e., phase alignment) for clock skew compensation by comparing phase difference using a phase detector ¶ [0045] )
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2003/0197537 (hereinafter, “Saint-Laurent”) in view of U.S. Publication No. 2014/0340130 (hereinafter, “Machnicki”) .
As per claim 4, Saint-Laurent does not distinctly disclose an apparatus wherein the backward clock network includes a plurality of multiplex circuits and a plurality of first buffer circuits, wherein a particular multiplex circuit of the plurality of multiplex circuits is configured to select, using a selection signal, between a first distributed clock signal of the plurality of distributed clock signals and a second distributed clock signal of the plurality of distributed clock signals to generate an intermediate clock signal, and wherein a particular buffer circuit of the plurality of first buffer circuits is configured to buffer the intermediate clock signal to generate a buffered clock signal.
However, Machnicki explicitly discloses the following:
an apparatus wherein the backward clock network includes a plurality of multiplex circuits and a plurality of first buffer circuits, wherein a particular multiplex circuit of the plurality of multiplex circuits is configured to select, using a selection signal, between a first distributed clock signal of the plurality of distributed clock signals and a second distributed clock signal of the plurality of distributed clock signals to generate an intermediate clock signal, and wherein a particular buffer circuit of the plurality of first buffer circuits is configured to buffer the intermediate clock signal to generate a buffered clock signal. (Fig. 4 illustrates a clock mesh generator 400 that includes multiplex circuits 407 through 409 and one or more buffers (not shown) may be used to drive each clock signal included in the clock mesh ¶ [0036] In other words, these circuits are configured to select one or more of the clocks with various frequencies and coupled the selected clocks to the clock mesh ¶ [0035] )
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Saint-Laurent and Machnicki because both references are in the same field of endeavor. Machnicki’s teaching of using a combination of multiplexers and buffers in selecting a clock for one or more processing blocks would enhance Saint-Laurent's system by allowing the system to implement a dynamic power consumption while at the same time minimizing the circuit design footprint.
Claim 10-11 are rejected under U.S.C. 103 as being unpatentable over U.S. Publication No. 2003/0197537 (hereinafter, “Saint-Laurent”) in view of U.S. Publication No. 2025/0334999 (hereinafter, “Arp”) .
As per claim 10, Saint-Laurent does not distinctly discloses wherein performing the first phase comparison includes: comparing a first rising edge of the global clock signal to a corresponding rising edge of the first back clock signal; and comparing a first falling edge of the global clock signal to a corresponding falling edge of the first back clock signal.
However, Arp explicitly discloses wherein performing the first phase comparison includes: comparing a first rising edge of the global clock signal to a corresponding rising edge of the first back clock signal; and comparing a first falling edge of the global clock signal to a corresponding falling edge of the first back clock signal. ( detecting skew by comparing rising and falling edges of clocks between a reference cock and local clock ¶ [0038] )
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Saint-Laurent and Arp because both references are in the same field of endeavor. Arp’s teaching of detecting skew by comparing rising and falling edges of clocks between a reference cock and local clock would enhance Saint-Laurent's system by synchronizing clock between multiple circuits, thus enhancing data transfer.
As per claim 11, Saint-Laurent as modified discloses a method further comprising: determining, by the control circuit, a frequency and a magnitude of a change in a voltage level of a power supply node using the first result; and modifying, by the clock generator circuit, the global clock signal based on the frequency and the magnitude. (Saint-Laurent: ¶ [0046] discloses voltage-controlled oscillator (VCO) 450 may finally generate an output clock that has been phase-corrected. Therefore, correcting the phase of a wave signal impact its magnitude. Indeed, see ¶ [0032] Further, The phase-detector detector 420 may compare the frequency of the reference clock and the frequency of the output clock (i.e., feedback clock that has been divided by N via the second divider 460) and produce an output that is proportional to the frequency different. ) & (ARP: setting 606 a target clock frequency in response to the deskewing. Once the deskew 604 process has completed, the digital devices are prepared to transition to an operational state. In some examples, each digital device 601, 603, 605, 607 is set to the target clock frequency for the operational state. In some implementations, the digital device 601, 603, 605, 607 set 606 the target clock frequency based on a received command, for example, from an operating system.; ¶ [0040] )
Claim 13 is rejected under 35 U.S..C. 103 as being unpatentable over U.S. Publication No. 2003/0197537 (hereinafter, “Saint-Laurent”) in view of U.S. Publication No. 2022/0206987 (hereinafter, “Bal”) .
As per claim 13, Saint-Laurent does not distinctly disclose a method wherein generating the global clock signal includes generating a plurality of phasors, wherein the plurality of phasors have different phases relative to the global clock signal, and wherein modifying the global clock signal includes: selecting a particular phasor of the plurality of phasors using the first result; and generating the global clock signal using the particular phasor.
However, Bal discloses a method wherein generating the global clock signal includes generating a plurality of phasors, wherein the plurality of phasors have different phases relative to the global clock signal, and wherein modifying the global clock signal includes: selecting a particular phasor of the plurality of phasors using the first result; and generating the global clock signal using the particular phasor.(Fig. 3 illustrates a clock generator having a p1 phase and p2 phase wherein the selection generation selecting between at least P1 phase and p2 phase)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Saint-Laurent and Bal because both references are in the same field of endeavor. Bal’s teaching of clock generator having a p1 phase and p2 phase wherein the selection generation selecting between at least P1 phase and p2 phase would enhance Saint-Laurent's system by matching phases between different circuits, thus enhancing data communication.
Claim(s) 14, 19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2018/0284878 (hereinafter, “Artieri”) in view of U.S. Publication No. 2003/0197537 (hereinafter, “Saint-Laurent”) .
As per claim 14, Artieri discloses a system, comprising:
a power circuit configured to generate a regulated voltage using an input voltage; (Fig. 1 illustrates a global power rail that generates a global voltage distribution to one or more power domain circuits)
a clock generator circuit configured to generate a global clock signal using the regulated voltage; (Global clock tree for generating global clock signals; Fig. 1)
Artieri does not distinctly discloses the following
a forward clock network configured to distribute the global clock signal to generate a plurality of distributed clock signals;
one or more logic circuits including a particular logic circuit configured to perform a particular operation using a particular distributed clock signal of the plurality of distributed clock signals and the regulated voltage;
a backward clock network configured to select the particular distributed clock signal to generate a first back clock signal; and a control circuit configured to perform a phase comparison between the global clock signal and the first back clock signal; and wherein the clock generator circuit is further configured to modify the global clock signal using a result of the phase comparison.
However, Saint-Laurent explicitly discloses the following:
a forward clock network configured to distribute the global clock signal to generate a plurality of distributed clock signals; (global clock to distribute from the master clock clock signals to devices 130A-130C; Fig 3)
one or more logic circuits including a particular logic circuit configured to perform a particular operation using a particular distributed clock signal of the plurality of distributed clock signals and the regulated voltage; (Fig. 3 illustrates processor nodes 130A-130N (where N refers to any number of peripheral nodes in the global clock distribution network 110) )
a backward clock network configured to select the particular distributed clock signal to generate a first back clock signal; and (feedback lines that can be used for phased adjustment of the master clock; ¶s [0037]-[0040], Fig 3)
a control circuit configured to perform a phase comparison between the global clock signal and the first back clock signal; and (¶[0032] discloses how the alignment control unit 230 may be used to control the VDE 220 to align the global clock signal (i.e., phase alignment) for clock skew compensation. This adjustment is performed by a detector that compares the frequency of the divided clock and the frequency of the local clock that has been fed back. ¶ [0045] )
wherein the clock generator circuit is further configured to modify the global clock signal using a result of the phase comparison. ( ¶ [0038] discloses how a local clock signal from the local clock region 150C may be returned to the master PLL 120 for master clock phase alignments, via feedback line 306 )
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Artieri and Saint-Laurent because both references are in the same field of endeavor. Saint-Laurent’s teaching of adjusting clocks would enhance Artieri 's system by eliminating clock skew, thus enhancing data commination between different circuits.
As per claim 18, Artieri as modified discloses a system wherein the control circuit is further configured to generate supply transient information using the result of the phase comparison, and ( Saint-Laurent : phase detector (PD) 140A-140N determines that the local clock signal at a particular local clock region 150 may be too fast or too slow, a digital signal may be generated and returned to a corresponding clock processor node 130A-130N controlling the particular local clock region 150 for clock delay adjustment and clock synchronization; ¶ [0033] )
wherein the power circuit is further configured to adjust the regulated voltage using the transient information. ( Saint-Laurent : phase detector (PD) 140A-140N determines that the local clock signal at a particular local clock region 150 may be too fast or too slow, a digital signal may be generated and returned to a corresponding clock processor node 130A-130N controlling the particular local clock region 150 for clock delay adjustment and clock synchronization; ¶ [0033] and control voltage to produce the final output clock ¶[0051]) & (Artieri: The controlling within a respective power domain includes distributing a local voltage to the circuit load of the respective power domain via a local power rail. The controlling also includes propagating a local clock signal to the circuit load of the respective power domain via a local clock tree. The controlling further includes adjusting the local voltage and the local clock signal of the respective power domain using the multiple global voltages and the global clock signal in accordance with a duty cycle corresponding to a timeslot including multiple time periods per timeslot; ¶ [0011])
As per claim 19, Artieri as modified discloses a system wherein to modify the global clock signal, the clock generator circuit is further configured, using the result of the phase comparison, to change a frequency of the global clock signal from a first frequency to a second frequency less than the first frequency. (¶ [00676]-[0067] discloses how processor are supplied with different frequencies that include higher and lower frequencies. Further, the system can adjust these frequencies to align the global clock signal (i.e., phase alignment) for clock skew compensation by comparing phase difference using a phase detector ¶ [0045] )
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2018/0284878 (hereinafter, “Artieri”) in view of U.S. Publication No. 2003/0197537 (hereinafter, “Saint-Laurent”) and further view of U.S. Publication No. 2023/0119235 (hereinafter, “Hutton”).
As per claim 17, Artieri as modified does not distinctly discloses wherein to modify the global clock signal, the clock generator circuit is further configured to skip at least one cycle in a plurality of cycles included in the global clock signal within a particular period of time.
However, Hutton discloses wherein to modify the global clock signal, the clock generator circuit is further configured to skip at least one cycle in a plurality of cycles included in the global clock signal within a particular period of time. (¶ [0093] Clock throttling by cycle skipping)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Artieri as modified and Hutton because all references are in the same field of endeavor. Hutton’s teaching of implementing clock throttling by cycle skipping would enhance Artieri 's as modified system by adjusting the power consumption of the system, thus enhancing power management.
Allowable Subject Matter
Claims 5, 8-9, 15-16, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
With respect to any newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See MPEP §714.02 and § 2163.06. For example, when responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov
1 As per independent claim 7, this method claim is substantially equivalent to apparatus claim 1.
Prosecution Insights