Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 7/07/2026 regarding the prior art rejections of Claims 1 - 23 have been fully considered but are moot because of the new ground of rejection. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.
EXAMINER’S AMENDMENT
An examiner’s amendment to the record appears below. Should the changes and/or additions be unacceptable to applicant, an amendment may be filed as provided by 37 CFR 1.312. To ensure consideration of such an amendment, it MUST be submitted no later than the payment of the issue fee.
The application has been amended as follows:
Claim 1: “An apparatus, comprising: processing circuitry associated with one or more memory devices and configured to cause the apparatus to: receive a write command that indicates data to be written for one or more memory cells of a memory system; initiate a write operation to write the data to the one or more memory cells based at least in part on the write command; polling the mode register to adjust a value of a mode register from a first value to a second value based at least in part on initiating the write operation, wherein the value of the mode register indicates whether the write operation is valid.”
Claim 18: “An apparatus, comprising: processing circuitry associated with one or more memory devices and configured to cause the apparatus to: receive a write command that indicates data to be written for one or more memory cells of a memory system; initiate a write operation to write the data to the one or more memory cells based at least in part on the write command; polling the mode register to adjust a value of a mode register from a first value to a second value based at least in part on initiating the write operation, wherein the value of the mode register indicates whether the write operation is valid.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 8 & 18 – 23 are rejected under 35 U.S.C. 103 as being unpatentable over Terada (US 2022/0254435) in view of Terada (US 2022/0277790 A1) in view of Terada (US 11775459 B2) in view of Bill (JP 2017162492 A).
In regards to claim 1, Terada teaches:
An apparatus, comprising: processing circuitry associated with one or more memory devices and configured to cause the apparatus to: receive a write command that indicates data to be written for one or more memory cells of a memory system; initiate a write operation to write the data to the one or more memory cells based at least in part on the write command; (0091, the controller 10 generates a patch on the basis of the read pointers and write data, and adds the patch to the write data (S1008). The patch is a correct value that is supposed to be originally recorded on the memory cell MC having a failure. Next, the controller 10 issues a write command to the nonvolatile memory 20 (S1009). Accordingly, the controller 10 issues write data to the nonvolatile memory 20. The write data has, for example, 320 bytes. The write data is divided into, for example, ten pages of 32 bytes, and is written to the nonvolatile memory 20.)
Terada fails to teach:
and adjust a value of a mode register from a first value to a second value based at least in part on initiating the write operation, wherein the value of the mode register indicates whether the write operation is valid.
However, Terada teaches:
and adjust a value of a mode register from a first value to a second value based at least in part on initiating the write operation, wherein the value of the mode register indicates whether the write operation is valid. (0311 & 0316, The signal of 4 bits outputted from the counter circuit is the number of fail bits (“Fail Bit Number” to be described in Table 3, and corresponds to one piece of memory cell information (see FIG. 6) inputted to the memory access control unit 511 through the signal input/output unit 523. The memory access control unit 511 records the inputted signal of 4 bits on the mode register 514 (see FIG. 6). The memory chip 31 according to the present embodiment includes sixteen memory banks 42. Accordingly, the mode register 514 has a storage region for 64 bits (=4 bits×16) for storing the number of fail bits. The microcontroller 53 is configured to count the number of fail bits with the counter circuit in both cases of the normal write operation process and the write operation process with disturb failure detection. The memory chip 31 decides which one of the normal write operation process and the write operation process with disturb failure detection is to be executed, on the basis of a command inputted from the memory controller 11 (see FIG. 1). Table 3 illustrates examples of commands to be transmitted from the memory controller 11 to the memory chip 31.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of handling memory cell errors of Terada with the teaching of Terada (US 2022/0277790 A1), which teaches a method of controlling a memory chip that make it possible to detect a disturb failure in order to improve memory devices. (Terada: 0004, Accordingly, performing rewriting of data to respond to a failure in writing of data and performing rereading of data to respond to an error in reading of data makes it possible to eliminate the error.)
In regards to claim 2, Terada in view of Terada teaches the apparatus of claim 1.
Terada teaches:
wherein the processing circuitry is further configured to cause the apparatus to: decode the write command based at least in part on receiving the write command, wherein, to adjust the value of the mode register, the processing circuitry is configured to cause the apparatus to: adjust the value of the mode register to the second value based at least in part on decoding the write command and initiating the write operation, wherein the second value indicates that the write operation is valid. (0081 & 0077, the ECC decoder 124 of the ECC processor 120 performs an error correction process on the data read out by the readout command and an error is detected. Accordingly, in a case where the returned value of the mode register readout command is other than 0, the detected disturb failure includes the UD failure;)
In regards to claim 3, Terada in view of Terada teaches the apparatus of claim 1.
Terada teaches:
wherein the processing circuitry is further configured to cause the apparatus to: complete the write operation based at least in part on initiating the write operation, wherein, to adjust the value of the mode register, the processing circuitry is configured to cause the apparatus to: adjust the value of the mode register to the second value based at least in part on completing the write operation, wherein the second value indicates that the write operation is valid. (0078 & 0096, where the controller 10 receives the returned value of the mode register readout command, the controller 10 determines, on the basis of the command, in a case where the controller 10 determines that the number of errors is equal to or greater than the first bit number (Yes in S1011), and is not equal to or greater than the second bit number;)
In regards to claim 4, Terada in view of Terada teaches the apparatus of claim 1.
Terada teaches:
wherein the processing circuitry is further configured to cause the apparatus to: receive, after adjusting the mode register back to the first value, a second write command that indicates second data to be written to one or more second memory cells of the memory system; and refrain from adjusting the value of the mode register from the first value to the second value based at least in part on a failure to decode the second write command, wherein the first value indicates that the write operation is invalid. (0077 & 0096, The mask command is a command to suppress application of a control voltage to the memory cells MC corresponding to mask data of “1” by a readout/write command subsequent to this command. That is, the controller 10 generates mask data that supplies “1” to the memory cells MC other than the memory cell MC that is determined to have the disturb failure in the sector, and issues a mask command accompanied by this mask data. Subsequently to issuing of the mask command, the controller 10 issues a fill zero command, and further issues a mode register readout command. The fill zero command is a command for writing “0” to all target memory cells MC. In addition, the mode register readout command is a command for returning, in a case where writing fails, the presence or absence (or the number) of the memory cells MC where writing fails. Accordingly, in a case where the returned value of the mode register readout command is other than 0, the detected disturb failure includes the UD failure.in a case where the controller 10 determines that the number of errors is equal to or greater than the first bit number (Yes in S1011), and is not equal to or greater than the second bit number;)
In regards to claim 5, Terada in view of Terada teaches the apparatus of claim 4.
Terada teaches:
wherein the processing circuitry is further configured to cause the apparatus to: receive, based at least in part on refraining from adjusting the value of the mode register, (0090, After reading out any of the pointers, the controller 10 issues a predetermined mask command, and masks a failure address indicated by the bit line pointer and the word line pointer (S1007). This stops application of an access voltage to the memory cells MC in a sector where the UD failure has occurred.)
Terada fails to teach:
a retransmission of the second write command that indicates the second data to be written to the one or more second memory cells of the memory system.
However, Bill teaches:
a retransmission of the second write command that indicates the second data to be written to the one or more second memory cells of the memory system. (94, wherein the retransmission includes retransmitting the determined plurality of write requests.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of handling memory cell errors of Terada with the teaching of Bill, which teaches a memory module that supports different types of memory protocols and supports different types of memory devices in order to improve memory devices. (Bill: Abstract, To provide a memory module that supports different types of memory protocols and supports different types of memory devices.)
In regards to claim 6, Terada in view of Terada teaches the apparatus of claim 1.
Terada fails to teach:
wherein the processing circuitry is further configured to cause the apparatus to: transmit, to a host device via a pin and based at least in part on adjusting the value of the mode register to the second value, a signal to indicate the validity of the write operation.
However, Bill teaches:
wherein the processing circuitry is further configured to cause the apparatus to: transmit, to a host device via a pin and based at least in part on adjusting the value of the mode register to the second value, a signal to indicate the validity of the write operation. (Fig. 3 and corresponding spec: FIG. 3 shows the arrangement of a plurality of pins on a memory module 8a, 8b having a host memory controller 6;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of handling memory cell errors of Terada with the teaching of Bill, which teaches a memory module that supports different types of memory protocols and supports different types of memory devices in order to improve memory devices. (Bill: Abstract, To provide a memory module that supports different types of memory protocols and supports different types of memory devices.)
In regards to claim 7, Terada in view of Terada in view of Bill teaches the apparatus of claim 6.
Terada further teaches:
wherein the pin comprises a decode status flag or an alert pin. (0064, The work memory 30 may be configured to include the working address translation table 310, the working pointer data 320, and an error flag 330;)
In regards to claim 8, Terada in view of Terada teaches the apparatus of claim 1.
Terada teaches:
wherein the first value comprises a first binary value of the mode register and the second value comprises a second binary value of the mode register. (0077, controller 10 generates mask data that supplies “1” to the memory cells MC; writing “0” to all target memory cells)
In regards to claim 18, Terada in view of Terada in view of Bill teaches the apparatus and corresponds to claim 1 as analyzed accordingly.
In regards to claim 19, Terada in view of Terada in view of Bill teaches the apparatus of claim 18 and corresponds to claim 2 as analyzed accordingly.
In regards to claim 20, Terada in view of Terada in view of Bill teaches the apparatus of claim 18 and corresponds to claim 3 as analyzed accordingly.
In regards to claim 21, Terada in view of Terada in view of Bill teaches the apparatus of claim 18 and corresponds to claim 4 as analyzed accordingly.
In regards to claim 22, Terada in view of Terada in view of Bill teaches the apparatus of claim 21 and corresponds to claim 5 as analyzed accordingly.
In regards to claim 23, Terada in view of Terada in view of Bill teaches the apparatus of claim 18 and corresponds to claim 7 as analyzed accordingly.
Claims 9 – 17 are rejected under 35 U.S.C. 103 as being unpatentable over Terada (US 2022/0254435) in view of DeBrosse (US 2016/0344427 A1) in view of Bill (JP 2017/162492 A).
In regards to claim 9, Terada teaches:
An apparatus, comprising: processing circuitry associated with one or more memory devices and configured to cause the apparatus to: transmit, from a host system, a write command that indicates data to be written to one or more memory cells of a memory system; poll a mode register of a memory system based at least in part on the write command, (23 & 48, DMA engine 116 may generate write or read requests in order to carry out DMA operations, which may be utilize an access channel 160 to access non-volatile memor(ies) 172. failed write handling engine 323 may poll for or otherwise obtain error or status information for a write operation (e.g., by sending a command to read an error mode register for a location in non-volatile memory to determine whether the write failed or succeeded).)
Terada fails to teach:
wherein a value of the mode register indicates whether a write operation at the memory system is valid; and determine, based at least in part on the value of the mode register;
However, DeBrosse teaches:
wherein a value of the mode register indicates whether a write operation at the memory system is valid; (0005 & 0020, Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition, where the write-back indicator is a discrete signal sent to a memory controller, and the at least one non-volatile memory device asserting the write-back indicator extends cycle timing monitored by the memory controller while the write-back indicator is asserted. Non-volatile memory can degrade over time, under thermal loads, or due to other effects such that one or more memory cell values can change from a ‘0’ to a ‘1’ or vice versa.) and determine, based at least in part on the value of the mode register; (0032, FIG. 6 illustrates an example of multiple write-back buffer entries 602 and an associated threshold 604 in accordance with an embodiment. With continued reference to FIG. 4, the write-back buffer 410 can include multiple write-back buffer entries 602 associated with addresses that resulted in an errant read. Rather than immediately notifying the memory controller 402 when at least one write-back is needed, the threshold 604 can be used to define a threshold number of the write-back buffer entries 602 to populate before notifying the memory controller 402 that a write-back is needed. In the example of FIG. 6, the threshold 604 is set to trigger notification upon populating write-back buffer entry number ‘M’, where ‘M’ is a number between a first entry number (i.e., entry 0) and a maximum entry number (i.e., entry N). Setting the threshold 604 to an intermediate value allows more time to elapse between write-back operations while leaving one or more additional buffer entries available should the memory controller 402 delay scheduling of the write-back command. The threshold 604 can be configurable as part of a mode register to any value between ‘0’ and ‘N’ in the example of FIG. 6.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of handling memory cell errors of Terada with the teaching of DeBrosse, which teaches a method for adaptive error correction in a memory system in order to optimize the performance of memory devices. (DeBrosse: 0002, adaptive error correction in a memory system)
Terada in view of DeBrosse fails to teach:
whether to issue a command to the memory system to perform a retransmission of the write command or a subsequent access command.
However, Bill teaches:
whether to issue a command to the memory system to perform a retransmission of the write command or a subsequent access command. (94, wherein the retransmission includes retransmitting the determined plurality of write requests.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of handling memory cell errors of Terada with the teaching of Bill, which teaches a memory module that supports different types of memory protocols and supports different types of memory devices in order to improve memory devices. (Bill: Abstract, To provide a memory module that supports different types of memory protocols and supports different types of memory devices.)
In regards to claim 10, Terada in view of DeBrosse in view of Bill teaches the apparatus of claim 9.
Terada teaches:
wherein the processing circuitry is further configured to cause the apparatus to: determine, based at least in part on polling the mode register, that the value of the mode register comprises a first value that indicates the write operation is valid; and reset the value of the mode register from the first value to a second value based at least in part on determining that the value of the mode register comprises the first value. (0077 & 0096, The mask command is a command to suppress application of a control voltage to the memory cells MC corresponding to mask data of “1” by a readout/write command subsequent to this command. That is, the controller 10 generates mask data that supplies “1” to the memory cells MC other than the memory cell MC that is determined to have the disturb failure in the sector, and issues a mask command accompanied by this mask data. Subsequently to issuing of the mask command, the controller 10 issues a fill zero command, and further issues a mode register readout command. The fill zero command is a command for writing “0” to all target memory cells MC. In addition, the mode register readout command is a command for returning, in a case where writing fails, the presence or absence (or the number) of the memory cells MC where writing fails. Accordingly, in a case where the returned value of the mode register readout command is other than 0, the detected disturb failure includes the UD failure.in a case where the controller 10 determines that the number of errors is equal to or greater than the first bit number (Yes in S1011), and is not equal to or greater than the second bit number;)
In regards to claim 11, Terada in view of DeBrosse in view of Bill teaches the apparatus of claim 9.
Terada teaches:
wherein, to determine whether to issue the command to the memory system, the processing circuitry is configured to cause the apparatus to: determine to transmit the subsequent access command to the memory system based at least in part on the value of the mode register indicating that the write operation is valid, wherein the subsequent access command comprises a read command that indicates the data to be read from the one or more memory cells or a second write command that indicates second data to be written to the one or more memory cells. (0051, upon reception of an access command from the unillustrated host via the host interface unit 40, the controller 10 performs control to access the nonvolatile memory 20 in accordance with the command, and issue or transmit a result of such access to the host.)
In regards to claim 12, Terada in view of DeBrosse in view of Bill teaches the apparatus of claim 9.
Terada teaches:
wherein, to determine whether to issue the command to the memory system, the processing circuitry is configured to cause the apparatus to: determine to transmit the retransmission of the write command to the memory system based at least in part on the value of the mode register comprising a second value that indicates the write operation is invalid. (0078 & 0096, where the controller 10 receives the returned value of the mode register readout command, the controller 10 determines, on the basis of the command, in a case where the controller 10 determines that the number of errors is equal to or greater than the first bit number (Yes in S1011), and is not equal to or greater than the second bit number;)
In regards to claim 13, Terada in view of DeBrosse in view of Bill teaches the apparatus of claim 12.
Terada teaches:
wherein the processing circuitry is further configured to cause the apparatus to: transmit an erase command to erase the data from the one or more memory cells based at least in part on the write operation being invalid; and transmit the retransmission of the write command based at least in part on the erase command. (0075, That is, in a case where the controller 10 issues the disturb failure detection command to a target sector of the nonvolatile memory 20, in response to this, the microcontroller 70 accesses the memory cells MC (bits) for each sector, and returns values thereof to the controller 10.)
In regards to claim 14, Terada in view of DeBrosse in view of Bill teaches the apparatus of claim 12.
Terada teaches:
wherein the processing circuitry is further configured to cause the apparatus to: pause execution of an application associated with the write command based at least in part on the write operation being invalid. (0090, stops application of an access voltage to the memory cells MC in a sector where the UD failure has occurred.)
In regards to claim 15, Terada in view of DeBrosse in view of Bill teaches the apparatus of claim 12.
Terada fails to teach:
wherein the processing circuitry is further configured to cause the apparatus to: disable an address space associated with the one or more memory cells based at least in part on the write operation being invalid, wherein the retransmission of the write command indicates the data to be written to one or more second memory cells of the memory system that are different than the one or more memory cells based at least in part on disabling the address space.
However, Bill teaches:
wherein the processing circuitry is further configured to cause the apparatus to: disable an address space associated with the one or more memory cells based at least in part on the write operation being invalid, wherein the retransmission of the write command indicates the data to be written to one or more second memory cells of the memory system that are different than the one or more memory cells based at least in part on disabling the address space. (Fig. 4 and corresponding spec: such as a specific error condition or interrupt or other functions; On at least one pin used for the at least one high address bit in response to determining that the plurality of high address bits are available to specify a second address space)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of handling memory cell errors of Terada with the teaching of Bill, which teaches a memory module that supports different types of memory protocols and supports different types of memory devices in order to improve memory devices. (Bill: Abstract, To provide a memory module that supports different types of memory protocols and supports different types of memory devices.)
In regards to claim 16, Terada in view of DeBrosse in view of Bill teaches the apparatus of claim 9.
Terada teaches:
wherein the processing circuitry is further configured to cause the apparatus to: determine, based at least in part on polling the mode register, that the value of the mode register comprises a first value that indicates the write operation is valid; and reset the value of the mode register from the first value to a second value based at least in part on determining that the value of the mode register comprises the first value. (0077 & 0096, The mask command is a command to suppress application of a control voltage to the memory cells MC corresponding to mask data of “1” by a readout/write command subsequent to this command. That is, the controller 10 generates mask data that supplies “1” to the memory cells MC other than the memory cell MC that is determined to have the disturb failure in the sector, and issues a mask command accompanied by this mask data. Subsequently to issuing of the mask command, the controller 10 issues a fill zero command, and further issues a mode register readout command. The fill zero command is a command for writing “0” to all target memory cells MC. In addition, the mode register readout command is a command for returning, in a case where writing fails, the presence or absence (or the number) of the memory cells MC where writing fails. Accordingly, in a case where the returned value of the mode register readout command is other than 0, the detected disturb failure includes the UD failure.in a case where the controller 10 determines that the number of errors is equal to or greater than the first bit number (Yes in S1011), and is not equal to or greater than the second bit number;)
In regards to claim 17, Terada in view of DeBrosse in view of Bill teaches the apparatus of claim 16 and corresponds to claim 7 as analyzed accordingly.
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
•Qawami (U.S. Patent Application Publication No. US 2014/0317474 A1) teaches methods and apparatus related to PCMS (Phase Change Memory with Switch) write error detection are described. In one embodiment, a first storage unit stores a single bit to indicate whether an error corresponding to a write operation in any of one or more PCMS devices has occurred. Also, one or more storage units each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCMS devices.
•TAKADA (U.S. Patent Application Publication No. US 2022/0059164 A1) teaches a memory device according to one embodiment includes a memory cell array, bit lines, amplifier units, a controller, and a register. The memory cell array includes a memory cell that stores data nonvolatilely. The bit lines are connected to the memory cell array. The sense amplifier units are connected to the bit lines, respectively. The controller performs a write operation. The register stores status information of the write operation. The memory cell array includes a first storage region specified by a first address. The plurality of sense amplifier modules include a buffer region capable of storing data.
• Kawasumi (U.S. Patent Application Publication No. US 2006/0171190 A1) teaches systems and methods for accessing data in a memory, where a register is provided to temporarily store data from a write operation and to make the data available for read operations that are performed immediately following the write operation and are directed to the same data. In one embodiment, a memory system includes an array of a first type of memory cells and a register having cells of a second type. The second type of cells is designed to stabilize data more quickly than the first type. Data is written concurrently into the memory array and the register. When a read operation is directed to the location of an immediately preceding write operation, the data is read from the register. When a read operation is directed to a location that is not coincident with an immediately preceding write operation, the data is read from the memory array.
Conclusion
Applicant's arguments filed 7/07/2026 regarding the prior art rejections of Claims 1 - 23 have been fully considered but are moot because of the new ground of rejection. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/ Primary Examiner, Art Unit 2111 9/23/2026
