CTNF 18/979,319 CTNF 100758 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1 – 8 & 18 – 23 are rejected under 35 U.S.C. 103 as being unpatentable over Terada (US 2022/0254435) in view of Prather (US 11775459 B2) in view of Bill (JP 2017162492 A) . In regards to claim 1, Terada teaches: and adjust a value of a mode register from a first value to a second value based at least in part on initiating the write operation, wherein the value of the mode register indicates a validity of the write operation. (0077, The fill zero command is a command for writing “0” to all target memory cells MC. In addition, the mode register readout command is a command for returning, in a case where writing fails, the presence or absence (or the number) of the memory cells MC where writing fails.) Terada fails to teach: An apparatus, comprising: processing circuitry associated with one or more memory devices and configured to cause the apparatus to: receive a write command that indicates data to be written for one or more memory cells of a memory system; initiate a write operation to write the data to the one or more memory cells based at least in part on the write command; However, Prather teaches: An apparatus, comprising: processing circuitry associated with one or more memory devices and configured to cause the apparatus to: receive a write command that indicates data to be written for one or more memory cells of a memory system; initiate a write operation to write the data to the one or more memory cells based at least in part on the write command; (12, When a write command is issued and a row address and a column address are timely supplied with the command, write data can be supplied to the data terminals DQ, DBI, and DMI;) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of handling memory cell errors of Terada with the teaching of Prather, which teaches a single command can trigger a memory device to perform multiple operations in order to improve memory devices. (Prather: 2, Improving memory devices, generally, may include increasing memory cell density, increasing read/write speeds or otherwise reducing operational latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics.) In regards to claim 2, Terada in view of Prather teaches the apparatus of claim 1. Terada teaches: wherein the processing circuitry is further configured to cause the apparatus to: decode the write command based at least in part on receiving the write command, wherein, to adjust the value of the mode register, the processing circuitry is configured to cause the apparatus to: adjust the value of the mode register to the second value based at least in part on decoding the write command and initiating the write operation, wherein the second value indicates that the write operation is valid. (0081 & 0077, the ECC decoder 124 of the ECC processor 120 performs an error correction process on the data read out by the readout command and an error is detected. Accordingly, in a case where the returned value of the mode register readout command is other than 0, the detected disturb failure includes the UD failure;) In regards to claim 3, Terada in view of Prather teaches the apparatus of claim 1. Terada teaches: wherein the processing circuitry is further configured to cause the apparatus to: complete the write operation based at least in part on initiating the write operation, wherein, to adjust the value of the mode register, the processing circuitry is configured to cause the apparatus to: adjust the value of the mode register to the second value based at least in part on completing the write operation, wherein the second value indicates that the write operation is valid. (0078 & 0096, where the controller 10 receives the returned value of the mode register readout command, the controller 10 determines, on the basis of the command, in a case where the controller 10 determines that the number of errors is equal to or greater than the first bit number (Yes in S1011), and is not equal to or greater than the second bit number;) In regards to claim 4, Terada in view of Prather teaches the apparatus of claim 1. Terada teaches: wherein the processing circuitry is further configured to cause the apparatus to: receive, after adjusting the mode register back to the first value, a second write command that indicates second data to be written to one or more second memory cells of the memory system; and refrain from adjusting the value of the mode register from the first value to the second value based at least in part on a failure to decode the second write command, wherein the first value indicates that the write operation is invalid. (0077 & 0096, The mask command is a command to suppress application of a control voltage to the memory cells MC corresponding to mask data of “1” by a readout/write command subsequent to this command. That is, the controller 10 generates mask data that supplies “1” to the memory cells MC other than the memory cell MC that is determined to have the disturb failure in the sector, and issues a mask command accompanied by this mask data. Subsequently to issuing of the mask command, the controller 10 issues a fill zero command, and further issues a mode register readout command. The fill zero command is a command for writing “0” to all target memory cells MC. In addition, the mode register readout command is a command for returning, in a case where writing fails, the presence or absence (or the number) of the memory cells MC where writing fails. Accordingly, in a case where the returned value of the mode register readout command is other than 0, the detected disturb failure includes the UD failure.in a case where the controller 10 determines that the number of errors is equal to or greater than the first bit number (Yes in S1011), and is not equal to or greater than the second bit number;) In regards to claim 5, Terada in view of Prather teaches the apparatus of claim 4. Terada teaches: wherein the processing circuitry is further configured to cause the apparatus to: receive, based at least in part on refraining from adjusting the value of the mode register, ( 0090, After reading out any of the pointers, the controller 10 issues a predetermined mask command, and masks a failure address indicated by the bit line pointer and the word line pointer (S1007). This stops application of an access voltage to the memory cells MC in a sector where the UD failure has occurred.) Terada fails to teach: a retransmission of the second write command that indicates the second data to be written to the one or more second memory cells of the memory system. However, Bill teaches: a retransmission of the second write command that indicates the second data to be written to the one or more second memory cells of the memory system. (94, wherein the retransmission includes retransmitting the determined plurality of write requests.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of handling memory cell errors of Terada with the teaching of Bill, which teaches a memory module that supports different types of memory protocols and supports different types of memory devices in order to improve memory devices. (Bill: Abstract, To provide a memory module that supports different types of memory protocols and supports different types of memory devices.) In regards to claim 6, Terada in view of Prather teaches the apparatus of claim 1. Terada fails to teach: wherein the processing circuitry is further configured to cause the apparatus to: transmit, to a host device via a pin and based at least in part on adjusting the value of the mode register to the second value, a signal to indicate the validity of the write operation. However, Bill teaches: wherein the processing circuitry is further configured to cause the apparatus to: transmit, to a host device via a pin and based at least in part on adjusting the value of the mode register to the second value, a signal to indicate the validity of the write operation. (Fig. 3 and corresponding spec: FIG. 3 shows the arrangement of a plurality of pins on a memory module 8a, 8b having a host memory controller 6;) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of handling memory cell errors of Terada with the teaching of Bill, which teaches a memory module that supports different types of memory protocols and supports different types of memory devices in order to improve memory devices. (Bill: Abstract, To provide a memory module that supports different types of memory protocols and supports different types of memory devices.) In regards to claim 7, Terada in view of Prather in view of Bill teaches the apparatus of claim 6. Terada further teaches: wherein the pin comprises a decode status flag or an alert pin. (0064, The work memory 30 may be configured to include the working address translation table 310, the working pointer data 320, and an error flag 330;) In regards to claim 8, Terada in view of Prather teaches the apparatus of claim 1. Terada teaches: wherein the first value comprises a first binary value of the mode register and the second value comprises a second binary value of the mode register. (0077, controller 10 generates mask data that supplies “1” to the memory cells MC; writing “0” to all target memory cells) In regards to claim 18, Terada in view of Prather in view of Bill teaches the apparatus and corresponds to claim 1 as analyzed accordingly. In regards to claim 19, Terada in view of Prather in view of Bill teaches the apparatus of claim 18 and corresponds to claim 2 as analyzed accordingly. In regards to claim 20, Terada in view of Prather in view of Bill teaches the apparatus of claim 18 and corresponds to claim 3 as analyzed accordingly. In regards to claim 21, Terada in view of Prather in view of Bill teaches the apparatus of claim 18 and corresponds to claim 4 as analyzed accordingly. In regards to claim 22, Terada in view of Prather in view of Bill teaches the apparatus of claim 21 and corresponds to claim 5 as analyzed accordingly. In regards to claim 23, Terada in view of Prather in view of Bill teaches the apparatus of claim 18 and corresponds to claim 7 as analyzed accordingly . 07-21-aia AIA Claim s 9 – 17 are rejected under 35 U.S.C. 103 as being unpatentable over Terada (US 2022/0254435) in view of Volpe (US 11048644 B1) in view of Bill (JP 2017/162492 A) . In regards to claim 9, Terada teaches: wherein a value of the mode register indicates a validity of a write operation at the memory system; (0077, The fill zero command is a command for writing “0” to all target memory cells MC. In addition, the mode register readout command is a command for returning, in a case where writing fails, the presence or absence (or the number) of the memory cells MC where writing fails.) Terada fails to teach: An apparatus, comprising: processing circuitry associated with one or more memory devices and configured to cause the apparatus to: transmit, from a host system, a write command that indicates data to be written to one or more memory cells of a memory system; poll a mode register of a memory system based at least in part on the write command; However, Volpe teaches: An apparatus, comprising: processing circuitry associated with one or more memory devices and configured to cause the apparatus to: transmit, from a host system, a write command that indicates data to be written to one or more memory cells of a memory system; poll a mode register of a memory system based at least in part on the write command, (23 & 48, DMA engine 116 may generate write or read requests in order to carry out DMA operations, which may be utilize an access channel 160 to access non-volatile memor(ies) 172. failed write handling engine 323 may poll for or otherwise obtain error or status information for a write operation (e.g., by sending a command to read an error mode register for a location in non-volatile memory to determine whether the write failed or succeeded).) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of handling memory cell errors of Terada with the teaching of Volpe, which teaches memory mapping implemented at the access device in order to optimize the performance of memory devices. (Volpe: 17, memory offers performance characteristics that provide different optimization opportunities for accessing and managing data stored thereon.) Terada in view of Volpe fails to teach: and determine, based at least in part on the value of the mode register, whether to issue a command to the memory system to perform a retransmission of the write command or a subsequent access command. However, Bill teaches: and determine, based at least in part on the value of the mode register, whether to issue a command to the memory system to perform a retransmission of the write command or a subsequent access command. (94, wherein the retransmission includes retransmitting the determined plurality of write requests.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of handling memory cell errors of Terada with the teaching of Bill, which teaches a memory module that supports different types of memory protocols and supports different types of memory devices in order to improve memory devices. (Bill: Abstract, To provide a memory module that supports different types of memory protocols and supports different types of memory devices.) In regards to claim 10, Terada in view of Volpe in view of Bill teaches the apparatus of claim 9. Terada teaches: wherein the processing circuitry is further configured to cause the apparatus to: determine, based at least in part on polling the mode register, that the value of the mode register comprises a first value that indicates the write operation is valid; and reset the value of the mode register from the first value to a second value based at least in part on determining that the value of the mode register comprises the first value. (0077 & 0096, The mask command is a command to suppress application of a control voltage to the memory cells MC corresponding to mask data of “1” by a readout/write command subsequent to this command. That is, the controller 10 generates mask data that supplies “1” to the memory cells MC other than the memory cell MC that is determined to have the disturb failure in the sector, and issues a mask command accompanied by this mask data. Subsequently to issuing of the mask command, the controller 10 issues a fill zero command, and further issues a mode register readout command. The fill zero command is a command for writing “0” to all target memory cells MC. In addition, the mode register readout command is a command for returning, in a case where writing fails, the presence or absence (or the number) of the memory cells MC where writing fails. Accordingly, in a case where the returned value of the mode register readout command is other than 0, the detected disturb failure includes the UD failure.in a case where the controller 10 determines that the number of errors is equal to or greater than the first bit number (Yes in S1011), and is not equal to or greater than the second bit number;) In regards to claim 11, Terada in view of Volpe in view of Bill teaches the apparatus of claim 9. Terada teaches: wherein, to determine whether to issue the command to the memory system, the processing circuitry is configured to cause the apparatus to: determine to transmit the subsequent access command to the memory system based at least in part on the value of the mode register indicating that the write operation is valid, wherein the subsequent access command comprises a read command that indicates the data to be read from the one or more memory cells or a second write command that indicates second data to be written to the one or more memory cells. (0051, upon reception of an access command from the unillustrated host via the host interface unit 40, the controller 10 performs control to access the nonvolatile memory 20 in accordance with the command, and issue or transmit a result of such access to the host.) In regards to claim 12, Terada in view of Volpe in view of Bill teaches the apparatus of claim 9. Terada teaches: wherein, to determine whether to issue the command to the memory system, the processing circuitry is configured to cause the apparatus to: determine to transmit the retransmission of the write command to the memory system based at least in part on the value of the mode register comprising a second value that indicates the write operation is invalid. (0078 & 0096, where the controller 10 receives the returned value of the mode register readout command, the controller 10 determines, on the basis of the command, in a case where the controller 10 determines that the number of errors is equal to or greater than the first bit number (Yes in S1011), and is not equal to or greater than the second bit number;) In regards to claim 13, Terada in view of Volpe in view of Bill teaches the apparatus of claim 12. Terada teaches: wherein the processing circuitry is further configured to cause the apparatus to: transmit an erase command to erase the data from the one or more memory cells based at least in part on the write operation being invalid; and transmit the retransmission of the write command based at least in part on the erase command. (0075, That is, in a case where the controller 10 issues the disturb failure detection command to a target sector of the nonvolatile memory 20, in response to this, the microcontroller 70 accesses the memory cells MC (bits) for each sector, and returns values thereof to the controller 10.) In regards to claim 14, Terada in view of Volpe in view of Bill teaches the apparatus of claim 12. Terada teaches: wherein the processing circuitry is further configured to cause the apparatus to: pause execution of an application associated with the write command based at least in part on the write operation being invalid. (0090, stops application of an access voltage to the memory cells MC in a sector where the UD failure has occurred.) In regards to claim 15, Terada in view of Volpe in view of Bill teaches the apparatus of claim 12. Terada fails to teach: wherein the processing circuitry is further configured to cause the apparatus to: disable an address space associated with the one or more memory cells based at least in part on the write operation being invalid, wherein the retransmission of the write command indicates the data to be written to one or more second memory cells of the memory system that are different than the one or more memory cells based at least in part on disabling the address space. However, Bill teaches: wherein the processing circuitry is further configured to cause the apparatus to: disable an address space associated with the one or more memory cells based at least in part on the write operation being invalid, wherein the retransmission of the write command indicates the data to be written to one or more second memory cells of the memory system that are different than the one or more memory cells based at least in part on disabling the address space. (Fig. 4 and corresponding spec: such as a specific error condition or interrupt or other functions; On at least one pin used for the at least one high address bit in response to determining that the plurality of high address bits are available to specify a second address space) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of handling memory cell errors of Terada with the teaching of Bill, which teaches a memory module that supports different types of memory protocols and supports different types of memory devices in order to improve memory devices. (Bill: Abstract, To provide a memory module that supports different types of memory protocols and supports different types of memory devices.) In regards to claim 16, Terada in view of Volpe in view of Bill teaches the apparatus of claim 9. Terada teaches: wherein the processing circuitry is further configured to cause the apparatus to: determine, based at least in part on polling the mode register, that the value of the mode register comprises a first value that indicates the write operation is valid; and reset the value of the mode register from the first value to a second value based at least in part on determining that the value of the mode register comprises the first value. (0077 & 0096, The mask command is a command to suppress application of a control voltage to the memory cells MC corresponding to mask data of “1” by a readout/write command subsequent to this command. That is, the controller 10 generates mask data that supplies “1” to the memory cells MC other than the memory cell MC that is determined to have the disturb failure in the sector, and issues a mask command accompanied by this mask data. Subsequently to issuing of the mask command, the controller 10 issues a fill zero command, and further issues a mode register readout command. The fill zero command is a command for writing “0” to all target memory cells MC. In addition, the mode register readout command is a command for returning, in a case where writing fails, the presence or absence (or the number) of the memory cells MC where writing fails. Accordingly, in a case where the returned value of the mode register readout command is other than 0, the detected disturb failure includes the UD failure.in a case where the controller 10 determines that the number of errors is equal to or greater than the first bit number (Yes in S1011), and is not equal to or greater than the second bit number;) In regards to claim 17, Terada in view of Volpe in view of Bill teaches the apparatus of claim 16 and corresponds to claim 7 as analyzed accordingly. Prior Art Made of Record The prior art mode of record and not relied upon is considered pertinent to Applicant’s disclosure: Boehm (US 11561891 B1): Methods, systems, and devices for adaptive user defined health indications are described. A host device may be configured to dynamically indicate adaptive health flags for monitoring health and wear information for a memory device. The host device may indicate, to a memory device, a first index. The first index may correspond to a first level of wear of a set of multiple indexed levels of wear for the memory device. The memory device may determine that a metric of the memory device satisfies the first level of wear and indicate, to the host device, that the first level of wear is satisfied. The host device may receive the indication that the first level of wear is satisfied and indicate, to the memory device, a second level of wear of the set of indexed levels of wear that is different than the first level of wear. • Harms (US 2021/0090681 A1): Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR PERRY whose telephone number is (571)272-6319. The examiner can normally be reached Monday - Friday 8:00 - 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached on (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /V.P./Examiner, Art Unit 2111 /GUERRIER MERANT/ Primary Examiner, Art Unit 2111 4/7/2026 Application/Control Number: 18/979,319 Page 2 Art Unit: 2111 Application/Control Number: 18/979,319 Page 3 Art Unit: 2111 Application/Control Number: 18/979,319 Page 4 Art Unit: 2111 Application/Control Number: 18/979,319 Page 5 Art Unit: 2111 Application/Control Number: 18/979,319 Page 6 Art Unit: 2111 Application/Control Number: 18/979,319 Page 7 Art Unit: 2111 Application/Control Number: 18/979,319 Page 8 Art Unit: 2111 Application/Control Number: 18/979,319 Page 9 Art Unit: 2111 Application/Control Number: 18/979,319 Page 10 Art Unit: 2111 Application/Control Number: 18/979,319 Page 11 Art Unit: 2111 Application/Control Number: 18/979,319 Page 12 Art Unit: 2111 Application/Control Number: 18/979,319 Page 13 Art Unit: 2111 Application/Control Number: 18/979,319 Page 14 Art Unit: 2111
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