Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1, 10 and 19.
b. Claims 1-20 are pending on the application.
Drawings
2. The drawings were received on 12/12/2024. These drawings are review and accepted by examiner.
Information Disclosure Statement
3. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 02/25/2025. The information disclosed therein was considered.
Specification
4. The disclosure is objected to because of the following informalities:
In the first paragraph of the specification, the status of the Parent is a divisional of U.S. Patent Application No. 17/812,612 should be updated; namely, it has matured into U.S. Patent No. 12,198,777. Appropriate correction is required.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1, 10 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Asami et al. (US Pub. 2022/0093169 A1; “Asami et al”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1, Asami et al in Figures 1-18 are directly discloses a memory system (a memory system 1, Figures 1-3) comprising:
one or more memories (a non-volatile memory 10 and a volatile memory 20, Fig. 1) comprising a set of memory cells (a memory chip 0 (10-0)….chip N (10-N), Fig. 1); and
processing circuitry (a memory controller 30, Fig. 1) coupled with the one or more memories (the non-volatile memory 10 and the volatile memory 20) and configured to cause the memory system (the memory system 1)(the memory controller 30 control the operation of the memory 10 and 20 in the memory system 1, Fig. 1) to:
write the set of memory cells (a chip 10-0 include a set of memory cell PB0, Fig. 2) using a first value for an offset for a threshold voltage of a set of threshold voltages that each represent a different multi-bit value (a temperature management information circuit 21 such as a storage area of the NAND flash memory 10 in which data has been store and information relating to temperature at which the data has been written are stored in association with each other in, Figs. 1-2);
determine, for the set of memory cells (a chip 10-0 include a set of memory cell PB0, Fig. 2) after writing to the set of memory cells, a value for a read window associated with a subset of the set of threshold voltages (a refresh reservation information circuit 22 such as writing data, which has been written in a storage area in the NAND memory 10 , into another storage area after executing an error , thereby reducing the number error to be detect in data when the data is read out, Figs. 1-2);
determine an updated value (a register circuit 12, Fig. 2) for the offset for the threshold voltage (a voltage generator circuit 16, Fig. 2) based at least in part on the value for the read window (the voltage generator 16 for use in a read/write/erase process and supplies the generate voltage to the memory cell array 17 during the operation of memory device 10-0); and
write the set of memory cells (a chip 10-0 include a set of memory cell PB0, Fig. 2) using the updated value (the register circuit 12) for the offset for the threshold voltage based at least in part on determining the updated value (the register circuit 12 includes the status STS signal is updated for an operation state and is transfer from the status register to the input/output circuit 11 based on instruction from the memory controller 30 and output to the memory controller 30, see at least in Figures 1-3, paragraph 0029 to paragraph 0067 and the related disclosures).
Regarding to independent claim 19, Asami et al in Figures 1-18 are directly discloses a non-transitory computer-readable medium storing instructions, wherein the instructions are executable by one or more processors to cause a memory system to: (a memory system 1, Figures 1-3) comprising:
write the set of memory cells (a chip 10-0 include a set of memory cell PB0, Fig. 2) using a first value for an offset for a threshold voltage of a set of threshold voltages that each represent a different multi-bit value (a temperature management information circuit 21 such as a storage area of the NAND flash memory 10 in which data has been store and information relating to temperature at which the data has been written are stored in association with each other in, Figs. 1-2);
determine, for the set of memory cells (a chip 10-0 include a set of memory cell PB0, Fig. 2) after writing to the set of memory cells, a value for a read window associated with a subset of the set of threshold voltages (a refresh reservation information circuit 22 such as writing data, which has been written in a storage area in the NAND memory 10 , into another storage area after executing an error , thereby reducing the number error to be detect in data when the data is read out, Figs. 1-2);
determine an updated value (a register circuit 12, Fig. 2) for the offset for the threshold voltage (a voltage generator circuit 16, Fig. 2) based at least in part on the value for the read window (the voltage generator 16 for use in a read/write/erase process and supplies the generate voltage to the memory cell array 17 during the operation of memory device 10-0); and
write the set of memory cells (a chip 10-0 include a set of memory cell PB0, Fig. 2) using the updated value (the register circuit 12) for the offset for the threshold voltage based at least in part on determining the updated value (the register circuit 12 includes the status STS signal is updated for an operation state and is transfer from the status register to the input/output circuit 11 based on instruction from the memory controller 30 and output to the memory controller 30, see at least in Figures 1-3, paragraph 0029 to paragraph 0067 and the related disclosures).
Regarding claim 10, they encompass the same scope of invention as that of claims 1 and 19, except they draft the invention in method format instead of apparatus format. Asami et al. teach all the necessary elements to perform the method of these claims. The aspects of the invention contained in claim 10, are therefore rejected in method format for the same reasons claims 1 and 19, were rejected in apparatus format, as discussed above in the prior paragraphs of the office action.
Allowable Subject Matter
6. Claims 2-9, 11-18 and 20, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claims 2-6, the prior art fails to tech or suggest the claimed limitations, namely, the processing circuitry is further configured to cause the memory system to: predict, for the set of memory cells, a second value for the read window based at least in part on the value for the read window, wherein the updated value for the offset for the threshold voltage is based at least in part on the second value for the read window, wherein the processing circuitry is further configured to cause the memory system to: predict an error rate for the set of memory cells based at least in part on the value for the read window, wherein the updated value for the offset for the threshold voltage is based at least in part on the error rate.
With respected to dependent claim 7, the prior art fails to tech or suggest the claimed limitations, namely, the processing circuitry is further configured to cause the memory system to: apply a machine learning model to the first value for the read window, wherein the updated value for the offset for the threshold voltage is based at least in part on applying the machine learning model to the first value.
With respected to dependent claim 8, the prior art fails to tech or suggest the claimed limitations, namely, the processing circuitry is further configured to cause the memory system to: determine, based at least in part on writing to the set of memory cells, that a threshold quantity of access operations has been performed on the set of memory cells; and perform a refresh operation on the set of memory cells based at least in part on determining that the threshold quantity of access operations has been performed on the set of memory cells, wherein the first value for the read window is determined based at least in part on performing the refresh operation.
With respected to dependent claim 9, the prior art fails to tech or suggest the claimed limitations, namely, the processing circuitry is further configured to cause the memory system to: determine a set of distribution curves for a subset of the set of threshold voltages based at least in part on writing the set of memory cells, wherein the first value is based at least in part on the set of distribution curves.
With respected to dependent claim 11, the prior art fails to tech or suggest the claimed limitations, namely, predicting, for the set of memory cells, a second value for the read window based at least in part on the value for the read window, wherein the updated value for the offset for the threshold voltage is based at least in part on the second value for the read window.
With respected to dependent claims 12-15, the prior art fails to tech or suggest the claimed limitations, namely, predicting an error rate for the set of memory cells based at least in part on the value for the read window, wherein the updated value for the offset for the threshold voltage is based at least in part on the error rate, determining that the error rate for the set of memory cells satisfies a threshold error rate, wherein the value for the offset is set based at least in part on the error rate satisfying the threshold error rate.
With respected to dependent claim 16, the prior art fails to tech or suggest the claimed limitations, namely, applying a machine learning model to the first value for the read window, wherein the updated value for the offset for the threshold voltage is based at least in part on applying the machine learning model to the first value.
With respected to dependent claim 17, the prior art fails to tech or suggest the claimed limitations, namely, determining, based at least in part on writing to the set of memory cells, that a threshold quantity of access operations has been performed on the set of memory cells; and performing a refresh operation on the set of memory cells based at least in part on determining that the threshold quantity of access operations has been performed on the set of memory cells, wherein the first value for the read window is determined based at least in part on performing the refresh operation.
With respected to dependent claim 18, the prior art fails to tech or suggest the claimed limitations, namely, determining a set of distribution curves for a subset of the set of threshold voltages based at least in part on writing the set of memory cells, wherein the first value is based at least in part on the set of distribution curves.
With respected to dependent claim 20, the prior art fails to tech or suggest the claimed limitations, namely, the instructions are further executable by the one or more processors to cause the memory system to: predict, for the set of memory cells, a second value for the read window based at least in part on the value for the read window, wherein the updated value for the offset for the threshold voltage is based at least in part on the second value for the read window.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Marelli et al (US. 2018/0033491 A1) discloses method and apparatus with background reference positing and local reference position.
Wieduwilt et al (US. 11,120,860 B1) discloses staggering refresh address counters of a number of memory device and related method device and sytem.
Shiino et al (US. 2012/0257453 A1) discloses nonvolatile semiconductor memory device.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
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/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov
Prosecution Insights