The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim(s) 2-21 has/have been examined.Claim(s) 16-19 and 21 is/are allowable.
Claim(s) 2-15 and 20 have been rejected.
Novel Subject Matter
Claims 16-19 and 21 are allowable.
Claims 8, 15 and 20 recite novel subject matter while being rejected as indefinite.
Within claims 8 and 15, within each claim as a whole the examiner deems the novel limitation to be comparing first data to second data and determining whether an error correction capability of the system is functioning based at least in part on the comparison.
Within claim 16, within the claim as a whole the examiner deems the novel limitation to be sending a fifth command to the memory device to read the first data from the first logical address, wherein, in response to the fifth command, the memory device is configured to (i) output the first data from the first physical address and (ii) attempt, using the ECC engine, to correct the intentionally injected error in the first data.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 2, 5-7, 9 and 12-14 are rejected are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5 and 6 of U.S. Patent 12,197,766. Although the claims at issue are not identical, they are not patentably distinct from each other as described below.
Regarding claim 2, this claim recites limitations found in claims 1, 5 and 6 of Patent 12,197,766.
Regarding claims 5-7, these claims each recite limitations found in claims 1, 5 and 6 of Patent 12,197,766. The claims additionally recite calculating and writing ECC data. Claim 8 of Patent 12,197,766 describes outputting ECC data. Additionally, reference Lam (US Patent 10,528,423) teaches a memory system in which ECC information is generated and stored in a second memory address that is internally established to be an offset from the data address (column 2 lines 15-29). The ECC data is generated by and retrieved by a system processor (Figure 2 and column 5 lines 31-44). Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the memory testing claimed by Patent 12,197,766 such that memory writes are accompanied by ECC written to a second memory address and later read, as taught by Lam. This modification would have been obvious because storage of ECC in a second memory address allows for ECC’s greater data accuracy (Lam column 1 lines 47-48) and protection of information in DRAM and memory controller interface (Lam column 5 lines 58-63).
Regarding claim 9 this claim recites limitations found in claim 2 and is rejected on the same grounds as claim 2.
Regarding claims 12-14, these claims recite limitations found in claims 5-7, respectively, and are respectively rejected on the same grounds as claims 5-7.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 6-8, 13-15 and 20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Note that dependent claims not specifically addressed below inherit the deficiency of the parent claim and do not remedy the issue.
Claim 6 line 3 recites the limitation “the second logical address”. This limitation lacks antecedent basis. The limitation is recited in claim 5, but that is not a parent claim.
Claim 12 line 3 recites the limitation “the first ECC data”. This limitation lacks antecedent basis.
Claim 13 line 3 recites the limitation “the second logical address”. This limitation lacks antecedent basis.
Claim 14 line 4 recites the limitation “the second ECC data”. This limitation lacks antecedent basis.
Claim 19 line 3 recites the limitation “the second logical address”. This limitation lacks antecedent basis.
Claim 20 line 4 recites the limitation “the second ECC data”. This limitation lacks antecedent basis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kraipak (PG-PUB 2018/0174665) in view of MacGarry (PG-PUB 2017/0371560) and Lee (PG-PUB 2020/0151070).
Regarding claim 2, Kraipak discloses a memory device comprising a memory array (Figure 1); and a host device coupled to the memory device (paragraph 19, a test access port controller allows a user to interface with a BIST controller to perform test sequence) and configured to:
send a second command to the memory device to perform a first operation to remap the first logical address from a first physical address to a second physical address (paragraph 20, a repair instruction maps a defective memory location to a spare column);
send a third command to the memory device to write second data to the first logical address, wherein the second data is different from the first data (paragraph 22, after a simulated fault has caused allocation of spare columns, test read and write operations are performed on the spare columns to ensure they are free of faults; the test read and write data written to the spare column is presumably different from normal usage values written to primary memory column).
Kraipak does not expressly disclose the device wherein the host is configured to:
send a first command to the memory device to write first data to a first logical address of the memory array;
send a fourth command to the memory device to perform a second operation to remap the first logical address from the second physical address to the first physical address; and
send a fifth command to the memory device to read the first data from the first logical address.
Kraipak teaches performing testing at selected time periods when regular requests use is stopped (paragraphs 32 and 33).
MacGarry ('560) teaches a testing system in which a BIST controller performs periodic checks on SRAM to determine any hard errors indicating faults in the operation of a SRAM cell (paragraph 53). During testing data values may be temporarily buffered elsewhere, then write and read accesses test the memory for a hard fault (paragraph 33).
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the BISRM testing disclosed by Kraipak such that the testing is performed periodically during other use, as taught by MacGarry. This modification would have been obvious because some emerging applications are highly sensitive to errors, and in such applications, it is advantageous to be able to perform such BIST testing periodically whilst the memory controller is being used, so that any faulty cells can be bypassed and no longer used (MacGarry paragraph 53).
Since the testing is performed periodically, it is both preceded by normal operation and followed by normal operation. The resulting system would therefore perform normal usage (reading and writing first data to an address, as by the claimed first command), followed by a test mode (when a remap operation is performed and a second physical address is written and read, as by the claimed second and third commands, and as taught by Kraipak as testing of the spare memory columns), followed by a return to normal mode (when a reverse remap operation is performed and the first data may be read again, as by the claimed fourth and fifth commands).
Kraipak does not expressly disclose the device wherein the operations to remap a logical address are soft post-package repair (sPPR) operations.
Lee teaches a memory device in which logical addresses of memory are mapped to physical addresses (claim 1 of the reference) and a post package repair mode is executed whereby a controller can map a logical address from a physical address of a failed row a physical address of a spare row of memory (see abstract).
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the BISRM testing disclosed by Kraipak such that logical addresses are utilized and a remapping is done for a logical address using post package repair, as taught by Lee. This modification would have been obvious because a logical address is the address recognized and used by the host to perform memory access operations and an internal mapping of a logical address to a different physical resource does not affect how the host interfaces with the memory device (Lee paragraph 18) while use of a sPPR procedure to perform the mapping allows for a quick but temporary remapping of a memory address (Lee paragraph 27).
Regarding claims 3-4, Kraipak in view of MacGarry and Lee discloses:
3. (New) The system of claim 2, wherein the first data comprises one or more intentionally injected errors relative to the second data (Kraipak paragraph 50, the written data is a data value that has injected error and is subsequently determined to indicate a faulty memory).
4. (New) The system of claim 3, wherein the one or more intentionally injected errors include a bit insertion, a bit deletion, or a bit inversion (Kraipak paragraphs 40-44, specific bit locations are set for faults; a bit fault is an inversion).
Regarding claims 9-11, these claims recite limitations found in claims 2-4, respectively, and are respectively rejected on the same grounds as claims 2-4.
Claims 5-7, and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kraipak in view of MacGarry, Lee and Lam (US Patent 10,528,423).
Regarding claim 5, Kraipak in view of MacGarry and Lee discloses the system of claim 2. Kraipak in view of MacGarry and Lee does not expressly disclose the system of claim 2, wherein the host device is further configured to:
calculate error correction code (ECC) data corresponding to the first data; and
send a sixth command to the memory device to write the ECC data to a second logical address of the memory array.
Lam teaches a memory system in which ECC information is generated and stored in a second memory address that is internally established to be an offset from the data address (column 2 lines 15-29). The ECC data is generated by and retrieved by a system processor (Figure 2 and column 5 lines 31-44).
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the memory testing disclosed by Kraipak in view of MacGarry and Lee such that memory writes are accompanied by ECC written to a second memory address, as taught by Lam. This modification would have been obvious because storage of ECC in a second memory address allows for ECC’s greater data accuracy (Lam column 1 lines 47-48) and protection of information in DRAM and memory controller interface (Lam column 5 lines 58-63).
Regarding claim 6, Kraipak in view of MacGarry and Lee discloses the system of claim 2. Kraipak in view of MacGarry and Lee does not expressly disclose the system of claim 2, wherein the host device is further configured to:
calculate error correction code (ECC) data corresponding to the second data; and
send a sixth command to the memory device to write the ECC data to the second logical address.
Lam teaches a memory system in which ECC information is generated and stored in a second memory address that is internally established to be an offset from the data address (column 2 lines 15-29). The ECC data is generated by and retrieved by a system processor (Figure 2 and column 5 lines 31-44).
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the memory testing disclosed by Kraipak in view of MacGarry and Lee such that memory writes are accompanied by ECC written to a second memory address, as taught by Lam. This modification would have been obvious because storage of ECC in a second memory address allows for ECC’s greater data accuracy (Lam column 1 lines 47-48) and protection of information in DRAM and memory controller interface (Lam column 5 lines 58-63).
Regarding claim 7, Kraipak in view of MacGarry, Lee and Lam discloses the system of claim 6, wherein the host device is further configured to:
send a seventh command to the memory device to read the ECC data from the second logical address; and
receive the ECC data from the memory device in response to the seventh command (Lam column 5 lines 34-59, ECC scrubbing and ECC bit correction are performed; these require reading the ECC data).
Claims 12-14 recite limitations found in claims 5-7, respectively, and are respectively rejected on the same grounds as claims 5-7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Haertel teaches a storage system in which logical addresses are translated into first and second physical addresses; ECC values are stored to secondary physical addresses. Kawai teaches a system in which ECC data is written to a corresponding address in a second flash memory that corresponds to the write address in a first flash memory.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH SCHELL whose telephone number is (571) 272-8186. The examiner can normally be reached on Monday through Friday 9AM-5:00PM (Pacific Time).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at (571) 272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. The fax phone number for the examiner is 571-273-8186. The examiner may be e-mailed at joseph.schell@uspto.gov though communications via e-mail are not permitted without a written authorization form (see MPEP 502.03).
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JS/JOSEPH O SCHELL/Primary Examiner, Art Unit 2114