Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
Drawings were received on 12 December 2024. These drawings are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 9, 10-12, and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liu et al. (US 6,735,537 B2; hereinafter “Liu”).
In re claim 1, Liu discloses a method (Figs. 3-17) of compensating for current reconstruction errors in a power conversion system (Fig. 1), the method comprising: applying a voltage command to an inverter (24); measuring a DC-link current flowing through a DC side of the inverter (Col 4 Lines 32-34: the single current sensing device 32 is positioned on the DC link between the power supply 22 and the switching circuit 24); and reconstructing a phase current on the basis of the DC-link current (Col 20 Equations 47-52), wherein the restoring of the phase current comprises replacing a zero vector section with an active vector section (shown in Figs. 3-4 and further explained in Col 4 Lines: 62-65: there are six active vector states (V1-V6) where current will flow through the DC link and two zero vector states (V0, V7) where no current will flow through the DC link), while maintaining symmetry of a switching waveform for a plurality of switching elements included in the inverter (Col 5 Lines 53-55: The patterns of the voltage pulse trains in FIG. 5 are symmetrical to a center axis 50 that represents a half pulse width period tp), and reconstructing an average current (Col 20 Lines 37-43: after the current measurements are sampled in block 158, the process proceeds to block 160. At block 160, the process may include a determination or calculation of the third current measurement based on the first current measurement and the second current measurement. This calculation may be done using relation (47) through (52)).
In re claim 2, Liu discloses a method (see rejection above), wherein the reconstructing of the phase current comprises splitting one of three-phase signals within a switching period in space vector pulse width modulation (shown in Figs. 8A-10, 12A-B, 14A-B, 16A-B).
In re claim 3, Liu discloses a method (see rejections above and Figs. 14A-B, 16A-B), wherein the splitting one of the three-phase signals comprises at least one of: splitting a phase signal corresponding to (v_h) to generate a first switching waveform (pw_h); splitting a phase signal corresponding to (v_m) to generate a second switching waveform (pw_m); and splitting a phase signal corresponding to (v_l) to generate a third switching waveform (pw_l).
In re claim 9, Liu discloses a method (see above rejections and Fig. 1), wherein the measuring of the current (i_dc_link) flowing through the DC side of the inverter (24) comprises measuring the current using a single DC-link current sensor (32) disposed between the inverter and a DC power source (22).
In re claim 10, Liu discloses a power conversion system (Figs. 1, 3-17) comprising: a voltage command generator (34) configured to apply a voltage command to an inverter; a current sensor (32) configured to measure a DC-link current (i_dc_link) flowing through a DC side of the inverter; and a phase current reconstruction unit configured to reconstruct a phase current on the basis of the DC-link current (Col 20 Equations 47-52), and wherein the phase current reconstruction unit comprises a current restoration error compensator configured to compensate for a current reconstruction error by replacing a zero vector section with an active vector section (shown in Figs. 3-4 and further explained in Col 4 Lines: 62-65: there are six active vector states (V1-V6) where current will flow through the DC link and two zero vector states (V0, V7) where no current will flow through the DC link), while maintaining symmetry of a switching waveform for a plurality of switching elements included in the inverter (Col 5 Lines 53-55: The patterns of the voltage pulse trains in FIG. 5 are symmetrical to a center axis 50 that represents a half pulse width period tp)and reconstructing an average current (Col 20 Lines 37-43: after the current measurements are sampled in block 158, the process proceeds to block 160. At block 160, the process may include a determination or calculation of the third current measurement based on the first current measurement and the second current measurement. This calculation may be done using relation (47) through (52)).
Claim 11 recites substantially limitations as claim 2, therefore, will be rejected under the same rationale as claim 2.
Claim 12 recites substantially limitations as claim 3, therefore, will be rejected under the same rationale as claim 3.
Claim 18 recites substantially limitations as claim 9, therefore, will be rejected under the same rationale as claim 9.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 6,735,537 B2; hereinafter “Liu”) in view of Itoh et al. (US 10778116 B2; hereinafter “Itoh”).
In re claim 4, Liu discloses a method (see rejections above and Figs. 14A-B, 16A-B), wherein the reconstructing of the phase current comprises applying two switching waveforms (pw_h and pw_m), among the first switching waveform, the second switching waveform, and the third switching waveform, and reconstructing the average current (shown in Fig. 17).
Liu does not disclose a method, wherein the reconstructing of the phase current comprises applying two switching waveforms alternately.
Whereas, Itoh discloses a similar method (see Figs. 5B, 10), wherein the reconstructing of the phase current comprises applying two switching waveforms (Sv’ and Sw’), among the first switching waveform, the second switching waveform, and the third switching waveform (Su’), and the average current (iDCave).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the effective filing date of the claimed invention to have modified the apparatus of Liu such that the reconstructing of the phase current comprises applying two switching waveforms alternately as shown by Itoh. The selection of switching waveforms would be a routine matter to the person of ordinary skill to lower switching loss, noise, and increase efficiency, as taught by Itoh, cited above.
Claim 13 recites substantially limitations as claim 4, therefore, will be rejected under the same rationale as claim 4.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 6,735,537 B2; hereinafter “Liu”) in view of Hoffman et al. (US 11539283 B1; hereinafter “Hoffman”).
In re claim 5, Liu discloses a method (see rejections above and Figs. 14A-B, 16A-B), wherein the reconstructing of the phase current comprises sampling an average current, thereby reconstructing the phase current.
Liu does not disclose a method that comprises sampling an average current at a center point of switching.
Whereas, Hoffman discloses a similar method (Figs. 3-8), wherein the reconstructing of the phase current comprises sampling a current at a center point of switching, thereby reconstructing the phase current (Col 16 Lines : In the double-update operating mode, the current is sampled both at the beginning and at the middle of the switching period 166 as represented by times t0 and t2, respectively).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the effective filing date of the claimed invention to have modified the apparatus of Liu such that sampling an average current at a center point of switching as shown by Hoffman. The selection of sampling an average current at a center point of switching would be a routine matter to the person of ordinary skill to lower switching loss, noise, and increase circuit value clarity, as taught by Hoffman, cited above.
Claim 14 recites substantially limitations as claim 5, therefore, will be rejected under the same rationale as claim 5.
Claims 6-8 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 6,735,537 B2; hereinafter “Liu”) in view of Lee. (US 9,595,904 B2; hereinafter “Lee”).
In re claim 6, Liu discloses a method (see rejections above), wherein the inverter is controlled on the basis of space vector pulse width modulation.
Liu does not disclose a method that comprises when an active vector application time of an output voltage command is shorter than a minimum active vector application time (Tmin), injecting a minimum voltage and measuring the DC-link current.
Whereas, Lee (US 9595904 B2) discloses a method (Figs. 1, 12-24), wherein the inverter (Fig. 1) is controlled on the basis of space vector pulse width modulation (20 in Fig. 12), and wherein the method further comprises, when an active vector application time of an output voltage command is shorter than a minimum active vector application time (Tmin) (Col 6 Lines 23-26: the second area may be defined by an area where a zero vector application time of the restoring voltage grows smaller than a zero vector application time of PWM voltage command), injecting a minimum voltage (Col 5 Lines 55-58: a command modification unit configured to determine an adjusting voltage and a restoring voltage using a minimum injection voltage based on the determined area and to modify the PWM voltage command) and measuring the DC-link current (shown in Fig. 9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the effective filing date of the claimed invention to have modified the apparatus of Liu such that an active vector application time of an output voltage command is shorter than a minimum active vector application time (Tmin), injecting a minimum voltage and measuring the DC-link current as shown by Lee. The selection of an active vector application time and injecting a minimum voltage would be a routine matter to the person of ordinary skill to lowers noise, and increases efficiency, as taught by Lee, cited above.
In re claim 7, Liu discloses a method (see above rejections)
Liu does not disclose a method, wherein the minimum voltage is a voltage equal to a minimum distance to a reconstructible area.
Whereas, Lee discloses a method, wherein the minimum voltage is a voltage equal to a minimum distance to a reconstructible area (shown in Fig. 16 and further explained in Col 5 Lines 55-61: command modification unit configured to determine an adjusting voltage and a restoring voltage using a minimum injection voltage based on the determined area and to modify the PWM voltage command, wherein the adjusting voltage is a voltage that has moved to a current detectable area, and the restoring voltage is a voltage that has compensated a difference of the adjusting voltage).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the effective filing date of the claimed invention to have modified the apparatus of Liu such that a minimum voltage is a voltage equal to a minimum distance to a reconstructible area as shown by Lee. The selection of a minimum voltage is a voltage equal to a minimum distance to a reconstructible area would be a routine matter to the person of ordinary skill to increase efficiency and safety, as taught by Lee, cited above.
In re claim 8, Liu discloses a method (see above rejections)
Liu does not disclose a method, comprising, after measuring the DC-link current, compensating for a voltage in the opposite direction of the minimum voltage to maintain the average voltage.
Whereas, Lee discloses a method, comprising, after measuring the DC-link current (Figs. 9 and 15), compensating for a voltage in the opposite direction of the minimum voltage to maintain the average voltage (shown in Fig. 18).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the effective filing date of the claimed invention to have modified the apparatus of Liu such that after measuring the DC-link current, compensating for a voltage in the opposite direction of the minimum voltage to maintain the average voltage as shown by Lee. The selection of after measuring the DC-link current, compensating for a voltage in the opposite direction of the minimum voltage to maintain the average voltage would be a routine matter to the person of ordinary skill to increase efficiency and accuracy, as taught by Lee, cited above.
Claim 15 recites substantially limitations as claim 6, therefore, will be rejected under the same rationale as claim 6.
Claim 16 recites substantially limitations as claim 7, therefore, will be rejected under the same rationale as claim 7.
Claim 17 recites substantially limitations as claim 8, therefore, will be rejected under the same rationale as claim 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Maeda et al. US 7411369 B2 Phase Current Detection Method, Inverter Control Method, Motor Control Method And Apparatus For Carrying Out These Methods
Wu et al. US 7495938 B2 DC Voltage Balance Control For Three-level NPC Power Converters With Even-order Harmonic Elimination Scheme
JIANG et al. CN 116191844 B Z-source Inverter Control Method And Device With Optimized Switch Loss And Common-mode Voltage Reduction
Hsieh et al. US 7898210 B2 To Obtain The Three-phase Current Via Adjusting Width Of Pulses With Single DC-link Current Sensor
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nicolas A Chapa Mills whose telephone number is (571)272-3683. The examiner can normally be reached Mon-Fri 9am-6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NICOLAS ALDEN CHAPA MILLS/ Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/ Supervisory Primary Examiner, Art Unit 2838
Prosecution Insights