DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawashima et al. (US 2020/0326570).
In regard to claim 1, Kawashima et al. teach a display comprising a plurality of pixel circuits (fig. 11), wherein each of the pixel circuits comprises: a display unit (fig. 7A element 114) receiving a first reference constant voltage (element 133 and paragraph 200) and coupled to a first node (fig. 5A NM); a first scanning transistor coupled to the first node and receiving a first scanning signal (element 101 receives scanning signal 121); an equivalent boosting capacitor coupled between the first node and a second node (element 104 between nodes NM and NB); a second scanning transistor coupled to the second node and receiving a second scanning signal (element 102 receives scanning signal 122); a third scanning transistor (element 106) coupled between the second node and a second reference constant voltage (Vref), and receiving the first scanning signal (element 106 receives scanning signal 121); and a storage capacitor coupled between the second node and the second reference constant voltage (element 105 is connected between nodes NB and NA. It is shown in fig. 5C that the node NA receives the second reference constant voltage Vref), wherein a first terminal of the storage capacitor is coupled to a first terminal of the third scanning transistor, and a second terminal of the storage capacitor is coupled to a second terminal of the third scanning transistor (fig. 5C the storage capacitor is coupled to every transistor and node in the device. The term coupled only requires the capacitor to be in the same device as the transistor), wherein during a first period of an image frame period, the first scanning transistor is turned on according to the first scanning signal to provide a first data voltage to the first node (fig. 5B, scan signal 121 is active which turns on transistor 101. The data signal Vdata1 is applied to node NM), while the third scanning transistor is turned on according to the first scanning signal to couple the second node to the second reference constant voltage (fig. 5B, Vref is on node NB), wherein during a second period of the image frame period subsequent to the first period, the second scanning transistor is turned on according to the second scanning signal to provide a second data voltage to the second node (figs. 5A and 5C. element 122 is active which activates element 102 putting Vdata2 on the second node NB), thereby boosting a voltage on the first node via the equivalent boosting capacitor (fig. 5C node NM is now the boosted voltage Vdata1+Vdata2).
In regard to claim 2, Kawashima et al. teach wherein a first terminal of the storage capacitor is coupled to a first terminal of the third scanning transistor (element 105 connected to element 106), and a second terminal of the storage capacitor is coupled to a second terminal of the third scanning transistor (fig. 5A the second terminal of the capacitor is couple to Vref through element 107. Vref is the second terminal of the third scanning transistor. Also, the entire device is coupled together).
In regard to claim 3, Kawashima et al. teach wherein the first reference constant voltage is the same as the second reference constant voltage (paragraph 200 states element 133 is 0V or ground. Paragraph 197 states Vref is either 0V, GND or a low potential. Kawashima et al. show that Vref can either be the same or a different voltage).
In regard to claim 4, Kawashima et al. teach wherein the first reference constant voltage is different from the second reference constant voltage (paragraph 200 states element 133 is 0V or ground. Paragraph 197 states Vref is either 0V, GND or a low potential. Kawashima et al. show that Vref can either be the same or a different voltage).
In regard to claims 5 and 15, Kawashima et al. teach wherein the first scanning transistor further receives a first data voltage, and the second scanning transistor further receives a second data voltage (elements 124, 125 and paragraph 75).
In regard to claims 6 and 16, Kawashima et al. teach wherein the first data voltage is the same as the second data voltage (paragraphs 116 and 122, Kawashima et al. teach Vdata1 and Vdata2 are equal to Vref).
In regard to claims 7 and 17, Kawashima et al. teach wherein the first data voltage is different from the second data voltage (paragraph 111, Kawashima et al. teach the first data being a negative. Fig. 2 shows Vdata2 being a positive value).
In regard to claims 8 and 18, Kawashima et al. teach wherein a voltage value of the first reference constant voltage and a voltage value of the second reference constant voltage are within a range of a voltage value of the first data voltage to a voltage value of the second data voltage (paragraphs 111 and 200. Kawashima et al. state the first data voltage can be negative. Fig. 2 shows Vdata2 being a positive value. Paragraphs 197 and 200 state Vref and element 133 or 0V which is between a positive and negative voltage).
In regard to claims 9 and 19, Kawashima et al. teach wherein during the first period the second scanning transistor is turned off according to the second scanning signal, and the third scanning transistor is turned on to provide the second reference constant voltage to the second node according to the first scanning signal (fig. 5C elements 101 and 106 are active and 102 is inactive), wherein during to the second period of the image frame period, the first scanning transistor and the third scanning transistor are turned off according to the first scanning signal (fig. 5C, element 121 is inactive).
In regard to claims 10 and 20, Kawashima et al. teach wherein during the second period, a first node voltage of the first node is boosted through the equivalent boosting capacitor (fig. 5C node NM is now the boosted voltage Vdata1+Vdata2) and the second node voltage of the second node is maintained through the storage capacitor and the second reference constant volage (fig. 5C, the voltage at node NB is maintained at Vdata2).
In regard to claim 11, Kawashima et al. teach wherein the first scanning transistor and the third scanning transistor are turned on during the same period (fig. 5A, elements 101 and 106 are connected to the same scanning line), and the first scanning transistor and the second scanning transistor are turned on during different periods (elements 101 and 102 are connected to different scanning lines).
In regard to claim 12, Kawashima et al. teach wherein each adjacent two of the pixel circuits share the same scanning signal line (fig. 11, elements 13[n,i] and 13[n, i+1] are connected to the same scan line 121).
In regard to claim 13, Kawashima et al. teach wherein the first node corresponds to a pixel electrode (fig. 8C, first node NM is connected to the pixel electrode of the liquid crystal 117), the display unit is disposed between the pixel electrode and an upper electrode (element 117 is a liquid crystal between two electrodes. See paragraph 200), and the upper electrode receives the first reference constant voltage (element 133 and paragraph 200. Element 133 is 0V or ground), wherein the display unit forms an equivalent pixel capacitor between the pixel electrode and the upper electrode (element 117. Liquid crystals are controlled by the voltage difference between two electrodes. These electrodes always form an equivalent capacitance).
In regard to claim 14, Kawashima et al. teach all the elements of claim 14 (see claim 1 rejection above) including wherein the driving method comprises: receiving a first reference constant voltage by the display unit (fig. 8B and C element 133); receiving a first scanning signal by the first scanning transistor and the third scanning transistor (element 121); and receiving a second scanning signal by the second scanning transistor (element 122).
Response to Arguments
Applicant's arguments filed 5/13/26 have been fully considered but they are not persuasive. Applicant argues on pages 9 and 10 that Kawashima et al. fail to teach the amendment to the independent claims. Kawashima et al. show the storage transistor 105 coupled in the pixel as shown in fig. 5A. The broadest reasonable interpretation of the limitation “coupled” is two elements being in the same device. Paragraph 28 of applicant’s specification gives an example of coupled as being electrically connected. This, however, does not constitute a definition. Absent a definition the term will be interpreted in the broadest reasonable manner.
Conclusion
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/JOSEPH R HALEY/ Primary Examiner, Art Unit 2621
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