Prosecution Insights
Last updated: October 02, 2026
Application No. 18/979,685

Ultra-wideband circuit

Final Rejection §103
Filed
Dec 13, 2024
Priority
Mar 27, 2024 — CN 202410362438.8
Examiner
BURD, KEVIN MICHAEL
Art Unit
2632
Tech Center
2600 — Communications
Assignee
Realtek Semiconductor Corporation
OA Round
2 (Final)
75%
Grant Probability
Favorable
3-4
OA Rounds
1y 1m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allowance Rate
586 granted / 783 resolved
+12.8% vs TC avg
Moderate +11% lift
Without
With
+11.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
22 currently pending
Career history
812
Total Applications
across all art units

Statute-Specific Performance

§101
5.2%
-34.8% vs TC avg
§103
48.4%
+8.4% vs TC avg
§102
22.2%
-17.8% vs TC avg
§112
10.7%
-29.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 783 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 1. This office action, in response to the amendment received 7/7/2026, is a final office action. Response to Amendments and Arguments 2. Claims 1 and 2 are amended to include new limitations to the claims. The rejections stated below address the newly added limitations. 3. New claims 12-16 are presented. Claims 12-16 are allowable as stated below. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 4. Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over West et al (US 10,749,258) in view of Sugino et al (US 2011/0069738). Regarding claim 1, West discloses an ultra-wideband (UWB) circuit (column 1, lines 10-33: Electrically large, multiple, independently steered, analog beam formers (ABF), that steer the beam of an active electronically scanned array (AESA) are challenging to implement in hardware due to the physical structure of multiple parallel banks of feed manifolds/phase shifters or ultra wide band (UWB) time delay units that are required for each beam. The circuit comprises UWB components. Therefore, the circuit is an UWB circuit.), comprising: a first pin (Figure 2: the first pin is located between antenna 262a and the corresponding selectable filtering filter.); a second pin (Figure 2: the second pin is located between antenna 262b and the corresponding selectable filtering filter.); a control register storing a plurality of control values (Figure 2: ASTR control); a baseband circuit coupled to the control register and configured to set the plurality of control values (Figure 2: ASTR control receives an input from another ASTR control which is located in processor 266. Figure 2 shows processor 266 operates at the digital domain. This is at baseband. Figure 2 shows the digital/baseband signal being converted to IF then to RF prior to transmission.); a switch coupled to the first pin (figure 2: the upper switch of COTS switches is connected to the first pin via the corresponding selectable filtering filter.); a transmission circuit coupled to the control register and the switch and configured to operate according to one of the plurality of control values (Figure 2: a transmission circuit path is shown. The signal to be transmitted will travel the transmission path and will receive a signal from the processor 266 (baseband circuit) to be input to the DAC 264 and ABF Tx 258 and COTS PAs. The power amplifiers receive a signal from the ASTR control.); a receiving circuit (Figure 2: a receive path is shown. The signal is received and travels via the ADCs 262 to the channelizer and beamformer of the processor 266 (baseband circuit). The receiving circuit comprises all of the components of this path.); a first low noise amplifier (LNA) coupled to the switch and the receiving circuit (Figure 2: the upper switch of the COTS switch is coupled to the upper LNA.); and a second LNA coupled to the second pin and the receiving circuit (Figure 2: the second switch, below the upper switch of the COTS switch, is coupled to the second LNA, below the upper LNA.); wherein the receiving circuit does not comprise the first LNA and the second LNA (Figure 2: the input signal will be provided to the LNAs and the mixers prior to being input to the receiving circuit comprising the ADCs 262 and the components downstream from the ADCs.). West does not disclose the receiving circuit coupled to the control register and configured to operate according to one of the plurality of control values. Sugino discloses the reception device as stated in the abstract. The reception device according to the present invention can reduce power consumption more using a UWB communication system (abstract). Figure 1 shows the circuit. Amplifier 2 and mixer 31b are external to a receiver circuit comprising the BPF 32. Pulse detector 33 will provide timing and control and band control signals to the BPF 32 such that the frequencies of the intermediate signal Sa corresponding to the interference waves and unnecessary waves are eliminated from the passband of the filter as stated in paragraph 0051. Figure 14 shows additional details of the circuit. Pulse detector 33 comprises the signal processor 33d. Paragraph 0120 discloses signal processor 33d performs specified arithmetic processing and a ROM stores the specified control program. Therefore, the pulse detector can be a control register configured to set a plurality of control values to operate the receiving circuit. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sugino into the circuit of West. Sugino discloses eliminating interference and unnecessary signal components from the passband of the filter according to the control values as stated in paragraph 0051. By removing unnecessary or unwanted signal components, the receiving device can operate more efficiently and effectively. Regarding claim 2, the combination discloses a first mixer coupled between the first LNA and the receiving circuit (West: Figure 2: an upper mixer receiving a LOrx1 will receive the signal from the upper LNA and will provide the mixed signal to the receiving circuit comprising the ADCs 262 and the components downstream from the ADCs. Sugino: figure 1: mixer 31b receives the signal from amplification unit 2 and provides the output of the mixer to the BPF 32.); and a second mixer coupled between the second LNA and the receiving circuit (West: Figure 2: the second mixer, below the upper mixer, will receive the signal from the second LNA, below the upper LNA, and will proved the mixed signal to the remaining components of the receiving circuit.); wherein the receiving circuit does not comprise the first mixer or the second mixer (West: figure 2: the upper and lower mixers provide output signals to the receiving circuit comprising the ADCs 262 and the components downstream from the ADCs. Sugino: figure 1: the mixer provides an output signal to the receiving circuit comprising the BPF 32.). Allowable Subject Matter 5. Claims 12-16 are allowed. 6. Claims 3-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Though West et al (US 10,749,258) mentions directional and omni-directional antennas as well as radar and sensing functions using antenna arrays in column 1, lines 10-33, the previously cited prior art does not disclose the specifics recited in claims 3-16. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN M. BURD whose telephone number is (571)272-3008. The examiner can normally be reached 9:30 - 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEVIN M BURD/Primary Examiner, Art Unit 2632 8/24/2026
Read full office action

Prosecution Timeline

Dec 13, 2024
Application Filed
Apr 15, 2026
Non-Final Rejection mailed — §103
Jul 07, 2026
Response Filed
Aug 26, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12750102
RADIOS CONFIGURED TO SPLIT POWER FOR A COMBINED SIGNAL, AND RELATED METHODS OF OPERATING RADIOS
1y 8m to grant Granted Sep 29, 2026
Patent 12739092
HIGH PRECISION TIMESTAMP DETECTION FOR IMPROVED CABLE MODEM CLOCK SYNCHRONIZATION
2y 8m to grant Granted Sep 15, 2026
Patent 12719513
SYSTEMS AND METHODS FOR MULTIBAND LINEARIZATION ARCHITECTURE USING KERNEL REGRESSION
2y 8m to grant Granted Aug 25, 2026
Patent 12712766
DATA AND CLOCK TRANSMISSION OVER A MAGNETIC CHANNEL
2y 6m to grant Granted Aug 18, 2026
Patent 12689407
TIMING DETECTION METHOD, COMMUNICATION SYSTEM AND RECEIVING APPARATUS
1y 9m to grant Granted Jul 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
75%
Grant Probability
86%
With Interview (+11.3%)
2y 11m (~1y 1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 783 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month