Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
1. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1 and 2 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by West et al (US 10,749,258).
Regarding claim 1, West discloses an ultra-wideband (UWB) circuit (column 1, lines 10-33: Electrically large, multiple, independently steered, analog beam formers (ABF), that steer the beam of an active electronically scanned array (AESA) are challenging to implement in hardware due to the physical structure of multiple parallel banks of feed manifolds/phase shifters or ultra wide band (UWB) time delay units that are required for each beam. The circuit comprises UWB components. Therefore, the circuit is an UWB circuit.), comprising:
a first pin (Figure 2: the first pin is located between antenna 262a and the corresponding selectable filtering filter.);
a second pin (Figure 2: the second pin is located between antenna 262b and the corresponding selectable filtering filter.);
a control register storing a plurality of control values (Figure 2: ASTR control);
a baseband circuit coupled to the control register and configured to set the plurality of control values (Figure 2: ASTR control receives an input from another ASTR control which is located in processor 266. Figure 2 shows processor 266 operates at the digital domain. This is at baseband. Figure 2 shows the digital/baseband signal being converted to IF then to RF prior to transmission.);
a switch coupled to the first pin (figure 2: the upper switch of COTS switches is connected to the first pin via the corresponding selectable filtering filter.);
a transmission circuit coupled to the control register and the switch and configured to operate according to one of the plurality of control values (Figure 2: a transmission circuit path is shown. The signal to be transmitted will travel the transmission path and will receive a signal from the processor 266 (baseband circuit) to be input to the DAC 264 and ABF Tx 258 and COTS PAs. The power amplifiers receive a signal from the ASTR control.);
a receiving circuit coupled to the control register and configured to operate according to one of the plurality of control values (Figure 2: a receive path is shown. The signal is received and travels along RX1-RX16 paths via the LNA, RCVR and ADCs 262 to processor 266 (baseband circuit). The receiving circuit comprises all of the components of this path. The low noise amplifiers receive a signal from the ASTR control.);
a first low noise amplifier (LNA) coupled to the switch and the receiving circuit (Figure 2: the upper switch of the COTS switch is coupled to the upper LNA which is a component of the receiving circuit. This LNA is coupled to the remaining components of the receiving circuit.); and
a second LNA coupled to the second pin and the receiving circuit (Figure 2: the second switch, below the upper switch of the COTS switch, is coupled to the second LNA, below the upper LNA, which is a component of the receiving circuit. This LNA is couped to the remaining components of the receiving circuit.).
Regarding claim 2, West discloses a first mixer coupled between the first LNA and the receiving circuit (Figure 2: an upper mixer receiving a LOrx1 will receive the signal from the upper LNA and will provide the mixed signal to the remaining components of the receiving circuit.); and a second mixer coupled between the second LNA and the receiving circuit (Figure 2: the second mixer, below the upper mixer, will receive the signal from the second LNA, below the upper LNA, and will proved the mixed signal to the remaining components of the receiving circuit.).
Allowable Subject Matter
3. Claims 3-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Though West et al (US 10,749,258) mentions directional and omni-directional antennas as well as radar and sensing functions using antenna arrays in column 1, lines 10-33, West does not disclose the specifics recited in claims 3-11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN M. BURD whose telephone number is (571)272-3008. The examiner can normally be reached 9:30 - 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KEVIN M BURD/Primary Examiner, Art Unit 2632 4/6/2026
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