DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 6 is objected to because of the following informalities: Lines 3-4 state: “…the multilayer body 10 is about…” Lines 3-4 should state: “…the multilayer body is about…”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7, 11, 14-17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hur et al. (US Publication 2011/0157767) in view of Yun et al. (US Publication 2020/0185153).
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Figure 2 of Hur with Examiner’s Comments (Figure 2EC)
In re claim 1, Hur discloses a multilayer ceramic electronic component comprising:
a multilayer body (110 – Figure 1, ¶22) including a plurality of laminated ceramic layers (¶23) and a plurality of laminated internal conductive layers (130a, 130b – Figure 2, ¶22), a first main surface and a second main surface opposed to each other in a height direction (top and bottom surfaces of 110 – Figure 2), a first lateral surface and a second lateral surface (front and back surfaces of 110 – Figure 1, Figure 2) opposed to each other in a width direction orthogonal or substantially orthogonal to the height direction (Figure 2), and a first end surface and a second end surface (left and right surfaces of 110 – Figure 2) opposed to each other in a length direction orthogonal or substantially orthogonal to the height direction and the width direction (Figure 2);
a first external electrode (120a – Figure 2, ¶22) on the first end surface (Figure 2); and
a second external electrode (120b – Figure 2, ¶22) on the second end surface (Figure 2);
wherein the first external electrode (120a – Figure 2) includes:
a first end surface-side external electrode (ES1 – Figure 2EC, ¶30) on the first end surface (Figure 2); and
a first main surface-side external electrode (MSE1 – Figure 2EC, ¶30) connected to the first end surface-side external electrode (ES1 – Figure 2EC) and provided on a portion of the first main surface and a portion of the second main surface each adjacent to the first end surface (Figure 2EC);
the second external electrode (120b – Figure 2) includes:
a second end surface-side external electrode (ES2 – Figure 2EC, ¶30) on the second end surface (Figure 2EC); and
a second main surface-side external electrode (MSE2 – Figure 2EC, ¶30) connected to the second end surface-side external electrode (ES2 – Figure 2EC) and provided on a portion of the first main surface and a portion of the second main surface each adjacent to the second end surface (Figure 2EC);
the first end surface-side external electrode (ES1 – Figure 2EC) and the second end surface-side external electrode (ES2 – Figure 2EC) each include an end surface-side base electrode layer (P1 and P2 of ES1, P1 and P2 of ES2 – Figure 2EC, ¶30),
the first main surface-side external electrode (MSE1 – Figure 2EC) and the second main surface-side external electrode (MSE2 – Figure 2EC) each include on the first main surface and the second main surface, a main surface-side base electrode layer (P2 of MSE1, P2 of MSE2 – Figure 2EC),
the end surface-side base electrode layer includes a first end surface-side base electrode layer with a high porosity (P1 of ES1, P1 of ES2 – Figure 2EC, ¶31-32) and a second end surface-side base electrode layer (P2 of ES1, P2 of ES2 – Figure 2EC, ¶31-32) with a porosity lower than that of the first end surface-side base electrode layer (Figure 2EC, ¶31-32); and
the main surface-side base electrode layer includes a layer (P2 of MSE1 – Figure 2EC) with a porosity lower than the porosity of the first end surface-side base electrode layer (P1 of ES1 – Figure 2EC) (¶31-32).
Hur does not disclose an end surface-side electrically conductive resin layer on the end surface-side base electrode layer, an end surface-side plated layer on the end surface-side electrically conductive resin layer, a main surface-side electrically conductive resin layer on the main surface-side base electrode layer, and a main surface-side plated layer on the main surface-side electrically conductive resin layer.
Yun discloses an end surface-side electrically conductive resin layer (131b, 131c, 132b, 132c on left/right surfaces of 110 – Figure 2, ¶28) on the end surface-side base electrode layer (131a, 132a on left/right surfaces of 110 – Figure 2, ¶28), an end surface-side plated layer (131d, 132d on left/right surfaces of 110 – Figure 2, ¶74) on the end surface-side electrically conductive resin layer (Figure 2), a main surface-side electrically conductive resin layer (131b, 131c, 132b, 132c on top/bottom surfaces of 110 – Figure 2) on the main surface-side base electrode layer (131a, 132a on top/bottom surfaces of 110 – Figure 2), and a main surface-side plated layer (131d, 132d on top/bottom surfaces of 110– Figure 2) on the main surface-side electrically conductive resin layer (Figure 2).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the conductive resin and plating layers as described by Yun to improve the mechanical strength of the electronic component and further preventing the penetration of plating liquid (¶7: Yun).
In re claim 2, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 1, as explained above. Hur further discloses wherein
the first external electrode (120a – Figure 2) includes a first lateral surface-side external electrode (120a on front and back surfaces of 110 – Figure 1, Figure 2) connected to the first end surface-side external electrode (ES1 – Figure 2EC, Figure 1) and provided on a portion of the first lateral surface and a portion of the second lateral surface (See Figure 1), each adjacent to the first end surface (Figure 1, Figure 2);
the second external electrode (120b – Figure 2) includes a second lateral surface-side external electrode (120b on front and back surfaces of 110 – Figure 1, Figure 2) connected to the second end surface-side external electrode (ES2 – Figure 2EC, Figure 1) and provided on a portion of the first lateral surface and a portion of the second lateral surface, each adjacent to the second end surface (Figure 1, Figure 2);
the first lateral surface-side external electrode and the second lateral surface-side external electrode each include, on the first lateral surface and the second lateral surface, a lateral surface-side base electrode layer (P1 and P2 of 120a on front and back surfaces of 110, P1 and P2 of 120b on front and back surfaces of 110 – Figure 2EC, Figure 1), and
the lateral surface-side base electrode layer includes a layer (P2 of 120a on front and back surfaces of 110, P2 of 120b on front and back surfaces of 110 – Figure 1, Figure 2) with a porosity lower than the porosity of the first end surface-side base electrode layer.(P1 of ES1, P1 of ES2 – Figure 2EC) (¶31-32).
Hur does not disclose a lateral surface-side electrically conductive resin layer on the lateral surface-side base electrode layer, and a lateral surface-side plated layer on the lateral surface-side electrically conductive resin layer.
Yun discloses a lateral surface-side electrically conductive resin layer (131b, 131c, 132b, 132c on surfaces 5, 6 – Figure 1, Figure 2, ¶31) on the lateral surface-side base electrode layer (131a, 132a on 5, 6 – Figure 1, Figure 2), and a lateral surface-side plated layer (131d, 132d on 5, 6 – Figure 1, Figure 2) on the lateral surface-side electrically conductive resin layer (Figure 1, Figure 2).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the conductive resin and plating layers as described by Yun to improve the mechanical strength of the electronic component and further preventing the penetration of plating liquid (¶7: Yun).
In re claim 3, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 1, as explained above. Hur further discloses wherein the second end surface-side base electrode layer (P2 of ES1, P2 of ES2 – Figure 2EC) is on the first end surface-side base electrode layer (P1 of ES1, P1 of ES1 – Figure 2EC).
In re claim 4, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 1, as explained above. Hur further discloses wherein the main surface-side base electrode layer (P2 of MSE1, P2 of MSE2 – Figure 2EC) is substantially continuous with the second end surface-side base electrode layer (P2 of ES1, P2 of ES2 – Figure 2EC).
In re claim 5, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 4, as explained above. Hur further discloses wherein the main surface-side base electrode layer (P2 of MSE1, P2 of MSE2 – Figure 2EC) is a single layer that is continuous with the second end surface-side base electrode layer (P2 of ES1, P2 of ES2 – Figure 2EC).
In re claim 7, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 1, as explained above. Hur further discloses wherein each of the plurality of ceramic layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component (¶24).
In re claim 11, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 1, as explained above. Hur further discloses each of the plurality of internal conductive layers (130a, 130b – Figure 2) includes Ni, Cu, Ag, Pd, or Au, or an alloy including at least one of Ni, Cu, Ag, Pd, or Au (¶15).
In re claim 14, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 1, as explained above. Hur further discloses wherein each end surface-side plated layer and the main surface-side plated layer includes a Ni plated layer, and a Sn plated layer on the Ni plated layer (¶52).
In re claim 15, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 2, as explained above. Hur further discloses wherein the lateral surface-side plated layer includes a Ni plated layer, and a Sn plated layer on the Ni plated layer (¶52).
In re claim 16, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 1, as explained above. Hur further discloses wherein each of the end surface-side base electrode layer (P1 and P2 of ES1, P1 and P2 of ES2 – Figure 2EC) and the main surface-side base electrode layer (MSE1, MSE2 – Figure 2EC) includes a metal component and at least one of a glass component or a ceramic component (¶14-15).
In re claim 17, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 16, as explained above. Hur further discloses wherein the metal component includes at least one of Cu, Ni, Ag, Pd, Ag-Pd alloy, or Au (¶15).
In re claim 19, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 16, as explained above. Hur further discloses wherein the ceramic component includes at least one of BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, or CaZrO3 (¶14-15; Note that the layer includes the glass component, as required by claim 16.).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hur et al. (US Publication 2011/0157767) in view of Yun et al. (US Publication 2020/0185153) and in further view of Lee et al. (US Publication 2015/0318109).
In re claim 6, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 1, as explained above. Hur does not disclose wherein a dimension in the length direction of the multilayer body is about 0.2 mm or more and about 10 mm or less;
a dimension of the multilayer body in the lamination direction is about 0.1 mm or more and about 10 mm or less; and
a dimension of the multilayer body in the width direction is about 0.1 mm or more and about 10 mm or less.
Lee discloses wherein a dimension in the length direction of the multilayer body is about 0.2 mm or more and about 10 mm or less (¶87);
a dimension of the multilayer body in the lamination direction is about 0.1 mm or more and about 10 mm or less (¶87); and
a dimension of the multilayer body in the width direction is about 0.1 mm or more and about 10 mm or less (¶87).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the dimensions of the component body to realize a device having a desired balance between capacitance characteristics and miniaturization characteristics per user specification, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hur et al. (US Publication 2011/0157767) in view of Yun et al. (US Publication 2020/0185153) and in further view of Park et al. (US Publication 2016/0307701).
In re claim 8, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 7, as explained above. Hur does not disclose wherein each of the plurality of ceramic layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound as a subcomponent.
Park discloses wherein each of the plurality of ceramic layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound as a subcomponent (¶52-53).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the secondary accessory ingredient to decrease the sintering temperature of the multilayer component and improve the high-temperature withstand voltage characteristics (¶54: Park).
Claim(s) 9-10 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hur et al. (US Publication 2011/0157767) in view of Yun et al. (US Publication 2020/0185153) and in further view of Lee et al. (US Publication 2015/0380159).
In re claim 9, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 1, as explained above. Hur does not explicitly disclose wherein a thickness of each of the plurality of ceramic layers is about 0.5 μm or more and about 15 μm or less.
Lee discloses wherein a thickness of each of the plurality of ceramic layers is about 0.5 μm or more and about 15 μm or less (¶89).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust a thickness of the dielectric layer to achieve a device having desired capacitance, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 10, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 1, as explained above. Hur does not explicitly disclose wherein a number of the plurality of ceramic layers is 10 or more and 700 or less.
Lee discloses wherein a number of the plurality of ceramic layers is 10 or more and 700 or less (¶89; Note that the ceramic layers are laminated with the internal electrodes.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the number of dielectric layers, and thus internal electrodes, to achieve a device having desired capacitance, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 12, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 1, as explained above. Hur does not disclose wherein a thickness of each of the plurality of internal conductive layers is about 0.2 μm or more and about 2.0 μm or less.
Lee discloses wherein a thickness of each of the plurality of internal conductive layers is about 0.2 μm or more and about 2.0 μm or less (¶89). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the internal electrode thickness to achieve a device having desired ESR characteristics, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 13, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 1, as explained above. Hur does not disclose wherein a number of the plurality of internal conductive layers is 10 or more and 700 or less.
Lee discloses wherein a number of the plurality of internal conductive layers is 10 or more and 700 or less (¶89).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the number of internal electrodes to achieve a device having desired capacitance, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hur et al. (US Publication 2011/0157767) in view of Yun et al. (US Publication 2020/0185153) and in further view of Tahara et al. (US Publication 2019/0180938).
In re claim 18, Hur in view of Yun discloses the multilayer ceramic electronic component according to claim 16, as explained above. Hur does not disclose wherein the glass component includes at least one of B, Si, Ba, Mg, Al, or Li.
Tahara discloses wherein the glass component includes at least one of B, Si, Ba, Mg, Al, or Li (¶31).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the glass component as described by Tahara to improve the densifying characteristics of the external electrode (¶31: Tahara).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Satoh et al. (US Publication 2018/0082792) [¶53], Figure 4
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/ARUN RAMASWAMY/ Primary Examiner, Art Unit 2847
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