DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/13/2024 and 06/26/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Keeth et al US 20190179769 and in view of Oh US 20230044654.
Regarding claim 1, Keeth teaches s semiconductor device (see figure 3, device 200) comprising:
at least one core die comprising a memory cell array (memory die 110-a, see para 0037, the memory dies may be an example of two-dimensional (2D) array of memory cells); and
a logic die communicating with the at least one core die via a plurality of through-silicon vias (TSVs) (see para 0038, The memory dies may include one or more vias (e.g., through-silicon vias (TSVs)). In some cases, the one or more vias may be part of internal signal paths that couple controllers with memory cells),
wherein the logic die comprises:
a memory controller configured to control a memory operation of the at least one core die (host device 105-a); and
a physical (PHY) region (translation device 205) configured to receive first input signals based on a first protocol from the memory controller and transmit first output signals of a second protocol generated based on the first input signals to the at least one core die via the plurality of TSVs (see para 0031, The translation device 205 may be configured to convert signals encoded using a communication scheme of the host device 105-a (also referred to as “HD communication scheme”) into signals encoded using a communication scheme of the memory device 110-a (also referred to as “MD communication scheme”) or vice-versa),
wherein the PHY region comprises a protocol converter (see figure 4, translation device 400 comprising translation component 415) configured to:
perform alignment processing on first bits of the first input signals so as to convert the first input signals from the first protocol into the first output signals of the second protocol (see para 0054, the translation component 415 may be configured to convert the data to a different symbol set based on the communication protocols being used. For example, the first communication protocol may use two-symbol modulation scheme (e.g., non-return to zero (NRZ) modulation scheme) where data is encoded using two symbols to represent one bit of data).
But Keeth fails to teach the second protocol is based on a multi-phase communication between the PHY region and the at least one core die.
However, Oh discloses a protocol converter to convert data to a multi-phase communication protocol for a memory device (see figure 9, four-phase converter 226, see para 0138).
Therefore, it would have been obvious to modify the protocol converter of Keeth and incorporate multi-phase protocol conversion.
The motivation for doing so is to provide compatibility with multi-phase protocol communication.
Regarding claim 2, Oh further teaches the first input signals comprise a first plurality of bits of write data, and the first output signals comprise the write data having multi-phases, and wherein the protocol converter is configured to perform a rearrangement operation on the first plurality of bits of the write data to communicate one or more bits of the write data using the multi-phases (see para 0138, The first to fourth internal clocks may be used for the read operation and the write operation in the I/O control circuit).
Regarding claim 3, Oh further teaches the PHY region is configured to sequentially transmit first to fourth pieces of write data respectively based four phases to the plurality of TSVs in synchronization with first to fourth internal clocks having phase differences of 90 degrees (see para 0138, the four-phase converter may generate first to fourth internal clocks in which phase differences with the synchronized data clock are 0 degree, 90 degrees, 180 degrees, and 270 degrees, respectively. The first to fourth internal clocks may be used for the read operation and the write operation in the I/O control circuit).
Regarding claim 7, the combination of Keeth and Oh further teaches the first input signals comprise a second plurality of bits of a command/address, and the first output signals comprise a command/address having multi-phases, and wherein the protocol converter is configured to perform a rearrangement operation on the second plurality of bits to communicate one or more bits of the second plurality of bits using the multi-phases (see Keeth’s para 0113, The data channel may also include at least one command/address (C/A) pin, also see Oh’s para 0138 discloses the four-phase conversion).
Regarding claim 9, Keeth further teaches the memory controller and the PHY region are configured to communicate the first input signals in synchronization with a first clock signal (see para 0121, The translation device 400 may also be configured to map clock signals), and wherein the first protocol comprises a protocol based on a double data rate (DDR) communication using the first clock signal (see para 0051, a memory device that implements a certain memory technology (e.g., HBM, HBM2, GDDR5x, etc.)).
Regarding claim 10, Keeth further teaches the at least one core die comprises a plurality of core dies (see figure 2, dies 235), and wherein the semiconductor device comprises a high-bandwidth memory (HBM) in which the plurality of core dies are vertically stacked above the logic die (see para 0051, a memory device that implements a certain memory technology (e.g., HBM, HBM2, GDDR5x, etc.)).
Allowable Subject Matter
Claims 11-20 are allowed.
Claims 4-6 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 4-6, the known prior arts fail to explicitly disclose “the PHY region further comprises first to fourth signal processing blocks configured to respectively output the first to fourth pieces of write data in synchronization with the first to fourth internal clocks, andwherein the protocol converter is further configured to output the one or more bits of the write data to each of the first to fourth signal processing blocks to determine a phase with which a plurality of bits of the write data are to be synchronized” in combination with other limitation found in the independent claims and the intervening claims.
Regarding claim 7, the known prior arts fail to explicitly disclose “the PHY region further comprises first to fourth signal processing blocks configured to output first to fourth commands/addresses having four phases in synchronization with first to fourth internal clocks having phase differences of 90 degrees, wherein the protocol converter is further configured to output one or more bits of the command/address to each of the first to fourth signal processing blocks, and wherein the one or more bits of the command/address determine a phase with which the second plurality of bits of the command/address are to be synchronized” in combination with other limitation found in the independent claims and the intervening claims.
Regarding claims 11-20, the known prior arts fail to explicitly disclose “a protocol converter configured to perform protocol conversion based on an alignment processing for rearranging first bits of a command/address provided from the memory controller; and first to N-th signal processing blocks configured to: process the rearranged bits of the command/address output from the protocol converter in synchronization with first to N-th internal clocks having multi-phases, and output the rearranged bits of the command/address having multi-phases, where N is an integer of two or more” in combination with other limitation found in the independent claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al US 20250266067 discloses a memory controller communicating with vertically stacked dies
Jin et al US 20220190936 discloses a translation device having a bit aligner to convert between two protocols
Chi et al US 20200142844 discloses a multiphase clock generator for a DDR physical PHY layer
Baeckler US 20150003477 discloses a central alignment circuitry for high-speed serial circuits
Fukaishi et al US 20030163606 discloses a high-speed memory system having a memory controller and a plurality of memories
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHONG H DANG whose telephone number is (571)272-0470. The examiner can normally be reached Monday-Friday 9:30AM - 6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at (571)272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PHONG H DANG/Primary Examiner, Art Unit 2184