Non-Final Rejection
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are rejected under 35 U.S.C. 103
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements filed on December 13th, 2024, and August 27th, 2025, have been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 6-11, 13-14, 16-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (U.S. Patent No. 12,524,000 B2), in view of Nautiyal et al. (U.S. Publication No. 2021/0397502 A1), hereinafter referred to as Nautiyal.
With regards to Claim 1, Wang teaches:
A System-on-Chip (SoC) comprising (Col. 18, Lines 16-21):
a plurality of SoC subsystems comprising a first management SoC subsystem and a first plurality of SoC subsystems connected together on a shared semiconductor substrate* (Col. 18, Lines 16-21; Col. 12, Lines 4-12; Fig. 6; Col. 6, Lines 22-27);
and a plurality of fault collection unit (FCU) instances deployed with at least one FCU instance at each SoC subsystem, where each FCU instance is configured to monitor one or more fault input signals at one or more fault inputs, to generate a local control signal for one or more hardware resources controlled by the FCU instance, and to escalate any … fault on a fault output (Fig. 6; Col. 12, Lines 4-12; Col. 18, Lines 37-41; Col. 15, Lines 17-20; Col. 2, Lines 37-47; Col. 18, Lines 54-61; Col. 17, Lines 24-40), where a first plurality of FCU instances deployed at the first plurality of SoC subsystems are each connected in a fault escalation tree with an escalation FCU instance deployed at the first management SoC subsystem by connecting the fault outputs from the first plurality of FCU instances to the one or more escalation fault inputs of the escalation FCU instance deployed at the first management SoC subsystem (Fig. 6, Col. 15, Lines 1-31; Col. 6, Lines 22-27; Col. 11, Line 65; Col. 12, Line 12).
Wang does not explicitly teach:
… unresolved …
However, Nautiyal teaches:
A System-on-Chip (SoC) comprising (Paragraph 0023):
a plurality of SoC subsystems comprising a first management SoC subsystem and a first plurality of SoC subsystems connected together on a shared semiconductor substrate* (Paragraphs 0023-0024);
and a plurality of fault collection unit (FCU) instances deployed with at least one FCU instance at each SoC subsystem, where each FCU instance is configured to monitor one or more fault input signals at one or more fault inputs, to generate a local control signal for one or more hardware resources controlled by the FCU instance, and to escalate any unresolved fault on a fault output, where a first plurality of FCU instances deployed at the first plurality of SoC subsystems are each connected in a fault escalation … with an escalation FCU instance deployed at the first management SoC subsystem by connecting the fault outputs from the first plurality of FCU instances to the one or more escalation fault inputs of the escalation FCU instance deployed at the first management SoC subsystem (Paragraphs 0011-0012, 0034, and 0039-0040).
*As defined by the attached reference, SuperMicro, “What Is System on a Chip?” it is inherent that subsystems on a SoC are connected on a single semiconductor substrate (Page 1, first paragraph).
Therefore, it would have been obvious to one of ordinary skill in the art in which said subject matter pertains to, prior to the effective filing date of the claimed invention, trigger escalation for unresolved faults in the system of Wang, as taught by Nautiyal, to appropriately handle faults accordingly (Nautiyal, Paragraph 0040).
With regards to Claim 2, Wang in view of Nautiyal teaches the system of Claim 1 as cited above. Wang in view of Nautiyal further teaches:
where a second plurality of FCU instances deployed at the first plurality of SoC subsystems are connected in a fault collection daisy-chain by connecting the fault output from each FCU instance in the second plurality of FCU instances to a fault input of succeeding FCU instance in the fault collection daisy-chain except for a terminating FCU instance in the fault collection daisy-chain which has a fault output connected to a fault input of the escalation FCU instance deployed at the first management SoC subsystem (Wang, Fig. 5-Fig. 6; Col. 6, Lines 22-27; Col. 11, Line 60 - Col. 12, Line 12; Col. 18, Lines 16-21; Col. 10, Lines 29-35).
With regards to Claim 4, Wang in view of Nautiyal teaches the system of Claim 1 as cited above. Wang in view of Nautiyal further teaches:
where each fault input signal received at a fault input of an FCU instance comprises a fault signal and an associated fault execution environment ID (EID) value which identifies a collection of hardware resources that perform a specified software function and that generated the fault signal (Wang, Col. 15, Lines 6-60; Col. 23, Lines 20-31, software).
With regards to Claim 6, Wang in view of Nautiyal teaches the system of Claim 1 as cited above. Wang in view of Nautiyal further teaches:
where a first fault input signal at a first fault input of a first FCU instance at a first SoC subsystem signals that a first fault is detected at one or more failing hardware resources of the first subsystem (Wang, Col. 15, Lines 6-60; Fig. 6; Col. 18, Lines 16-21; Col. 18, Lines 37-41).
With regards to Claim 7, Wang in view of Nautiyal teaches the system of Claim 6 as cited above. Wang in view of Nautiyal further teaches:
where the first FCU instance is further configured to monitor the first fault input signal to detect if the first fault was handled by a first execution environment (EENV) which owns the one or more failing hardware resources within a specified time window (Nautiyal, Paragraphs 0011-0012, 0024, and 0034).
With regards to Claim 8, Wang in view of Nautiyal teaches the system of Claim 7 as cited above. Wang in view of Nautiyal further teaches:
where the escalation FCU instance deployed at the first management SoC subsystem is configured to monitor the one or more escalation fault inputs and to generate a fault escalation signal to a managing execution environment (MEENV) which manages one or more EENVs (Wang, Fig. 6; Col. 15, Lines 17-47; Col. 17, Lines 9-40; Col. 2, Lines 37-47; Col. 18, Lines 54-61) when the first EENV has not handled the first fault (Nautiyal, Paragraphs 0011-0012, 0034, and 0039-0040).
With regards to Claim 9, Wang teaches:
A fault collection and reaction method for a system-on-chip (SoC) comprising a plurality of SoC subsystems with a plurality of fault collection unit (FCU) instances deployed with at least one FCU instance at each SoC subsystem, the fault collection and reaction method comprising (Col. 18, Lines 16-21; Col. 12, Lines 4-12; Fig. 6; Col. 6, Lines 22-27; Col. 2, Lines 37-47):
generating a first fault signal by one or more hardware resources at a first SoC subsystem in response to a first fault (Fig. 6; Col. 17, Lines 24-40);
providing the first fault signal to a first FCU instance at the first SoC subsystem and to a first execution environment (EENV) which owns the one or more failing hardware resources at the first SoC subsystem (Fig. 6; Col. 17, Lines 24-40; Col. 15, Lines 48-60);
monitoring, at a first fault input of the first FCU instance, the first fault signal (Fig. 6; Col. 17, Lines 24-40) …;
and generating, by the first FCU instance, a first fault output signal (Fig. 6; Col. 17, Lines 24-40) …;
and providing, over a first fault output of the first FCU instance, the first fault output signal to a second FCU instance at one of the plurality of SoC subsystems (Fig. 6; Col. 17, Lines 24-40).
Wang does not explicitly teach:
… to detect if the first EENV handles the first fault within a specified fault handling time interval;
… if the first FCU instance detects that the first EENV does not handle the first fault within the specified fault handling time interval;
However, Nautiyal teaches:
A fault collection and reaction method for a system-on-chip (SoC) comprising a plurality of SoC subsystems with a plurality of fault collection unit (FCU) instances deployed with at least one FCU instance at each SoC subsystem (Paragraphs 0023-0024), the fault collection and reaction method comprising:
monitoring, at a first fault input of the first FCU instance, the first fault signal to detect if the first EENV handles the first fault within a specified fault handling time interval (Paragraphs 0011-0012, 0034, 0039-0040);
and generating, by the first FCU instance, a first fault output signal if the first FCU instance detects that the first EENV does not handle the first fault within the specified fault handling time interval (Paragraphs 0011 and 0034);
and providing, over a first fault output of the first FCU instance, the first fault output signal to a second FCU instance at one of the plurality of SoC subsystems (Paragraphs 0039-0041 and 0011).
Therefore, it would have been obvious to one of ordinary skill in the art in which said subject matter pertains to, prior to the effective filing date of the claimed invention, trigger escalation for faults via timeout in the system of Wang, as taught by Nautiyal, to enable different fault reactions and appropriately handle faults accordingly (Nautiyal, Paragraph 0040).
With regards to Claim 10, Wang in view of Nautiyal teaches the method of Claim 9 as cited above. Wang in view of Nautiyal further teaches:
where the second FCU instance is an escalation FCU instance that is connected in a fault escalation tree with the first FCU instance, and where first fault output signal generated by the first FCU instance is provided to the escalation FCU instance that is deployed at a first management SoC subsystem for the plurality of SoC subsystems (Wang, Fig. 6; Col. 15, Lines 17-47; Col. 17, Lines 9-40; Col. 2, Lines 37-47; Col. 12, Lines 4-12).
With regards to Claim 11, Wang in view of Nautiyal teaches the method of Claim 9 as cited above. Wang in view of Nautiyal further teaches:
where the first fault output signal generated by the first FCU instance is provided to a second FCU instance at a second SoC subsystem connected in a daisy-chain with the first FCU instance to collect and monitor faults from the first and second SoC subsystems (Wang, Fig. 5-Fig. 6; Col. 6, Lines 22-27; Col. 11, Line 60 - Col. 12, Line 12; Col. 18, Lines 16-21; Col. 10, Lines 29-35).
With regards to Claim 13, Wang in view of Nautiyal teaches the method of Claim 9 as cited above. Wang in view of Nautiyal further teaches:
where the first FCU instance is connected and configured to monitor a plurality of fault signals at a plurality of fault inputs, to generate a local control signal for one or more hardware resources controlled by the first FCU instance, and to escalate any unresolved fault on the first fault output (Wang, Fig. 6; Col. 15, Lines 17-47; Col. 17, Lines 9-40; Col. 2, Lines 37-47; Col. 18, Lines 54-61; Nautiyal, Paragraphs 0011-0012, 0034, and 0039-0040).
All limitations of Claim 14 have been addressed in the analysis of Claim 4. Please see the above rejections for further details.
With regards to Claim 16, Wang in view of Nautiyal teaches the method of Claim 10 as cited above. Wang in view of Nautiyal further teaches:
monitoring, by the escalation FCU instance, a plurality of fault outputs generated by the first FCU instance and one or more additional FCU instances (Wang, Col. 11, Line 60 - Col. 12, Line 12; Fig. 6; Col. 15, Lines 17-47; Col. 17, Lines 9-40; Col. 2, Lines 37-47; Col. 18, Lines 54-61);
and generating, by the escalation FCU instance, a fault escalation signal to a managing execution environment (MEENV) which manages one or more execution environments (EENVs) when the first EENV has not handled the first fault (Nautiyal, Paragraphs 0011-0012, 0034, and 0039-0040).
With regards to Claim 17, Wang teaches:
A fault collection and handling system for a system-on-chip (SoC) comprising a plurality of SoC subsystems, the fault collection and handling system comprising (Col. 18, Lines 16-21; Col. 12, Lines 4-12; Fig. 6; Col. 6, Lines 22-27; Col. 2, Lines 37-47):
a first plurality of fault collection unit (FCU) instances deployed with at least one FCU instance at each of the plurality of SoC subsystems (Fig. 6; Col 11, Line 65-Col. 12, Line 3; Col. 2, Lines 37-47; Col. 17, Lines 24-40);
and an escalation FCU instance deployed at a first management SoC subsystem, where each of the first plurality of FCU instances comprises one or more fault inputs and a fault output (Fig. 6; Col. 15, Lines 6-22; Col. 16, Lines 48-57; Col. 17, Lines 24-40; Col 11, Line 65-Col. 12, Line 3) and is configured to monitor one or more fault input signals at the one or more fault inputs (Fig. 6; Col. 17, Lines 24-40; Col. 18, Lines 16-53), to generate a local control signal for one or more hardware resources controlled by the FCU instance (Col. 18, Lines 54-61; Col. 17, Lines 24-40; Col. 15, Lines 47-60), and to generate a fault output signal to escalate any … fault on the fault output (Col. 15, Lines 6-60, backtrack based on addresses and signals; Col. 16, example tables), and where the first plurality of FCU instances is connected in a fault escalation tree with the escalation FCU instance by connecting the fault outputs from the first plurality of FCU instances to the one or more escalation fault inputs of the escalation FCU instance (Fig. 6; Col. 15, Lines 6-22; Col. 16, Lines 48-57; Col. 17, Lines 24-40; Col 11, Line 65-Col. 12, Line 3).
Wang does not explicitly teach:
… unresolved …
However, Nautiyal teaches:
A fault collection and handling system for a system-on-chip (SoC) comprising a plurality of SoC subsystems (Paragraphs 0023-0024), the fault collection and handling system comprising:
a first plurality of fault collection unit (FCU) instances deployed with at least one FCU instance at each of the plurality of SoC subsystems (Paragraphs 0011-0012 and 0039-0040);
and an escalation FCU instance deployed at a first management SoC subsystem, where each of the first plurality of FCU instances comprises one or more fault inputs and a fault output and is configured to monitor one or more fault input signals at the one or more fault inputs, to generate a local control signal for one or more hardware resources controlled by the FCU instance (Paragraphs 0011-0012 and 0039-0040), and to generate a fault output signal to escalate any unresolved fault on the fault output (Paragraphs 0011-0012, 0034, and 0039-0040), and where the first plurality of FCU instances is connected in a fault escalation … with the escalation FCU instance by connecting the fault outputs from the first plurality of FCU instances to the one or more escalation fault inputs of the escalation FCU instance (Paragraphs 0034 and 0039-0040).
Therefore, it would have been obvious to one of ordinary skill in the art in which said subject matter pertains to, prior to the effective filing date of the claimed invention, trigger escalation for unresolved faults in the system of Wang, as taught by Nautiyal, to appropriately handle faults accordingly (Nautiyal, Paragraph 0040).
All limitations of Claim 18 have been addressed in the analysis of Claim 2. Please see the above rejections for further details.
With regards to Claim 20, Wang in view of Nautiyal teaches the system of Claim 17 as cited above. Wang in view of Nautiyal further teaches:
where each of the one or more fault input signals comprises a fault signal and an associated fault execution environment ID (EID) value which identifies a collection of hardware resources that perform a specified software function and that generated the fault signal (Wang, Col. 15, Lines 6-60; Col. 23, Lines 20-31, software), and where the fault output signal comprises a fault signal and an associated fault execution environment ID (EID) value which identifies a collection of hardware resources that perform a specified software function and that generated the fault signal (Col. 15, Lines 6-60, backtrack based on addresses and signals; Col. 16, example tables; Col. 23, Lines 20-31, software).
Claims 3, 5, 12, 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Nautiyal, in further view of Pedersen (U.S. Publication No. 2013/0226498 A1).
With regards to Claim 3, Wang in view of Nautiyal teaches the system of Claim 1 as cited above. Pedersen teaches the following limitation not explicitly taught by Wang in view of Nautiyal:
where each FCU instance is further configured to generate an overflow signal at an overflow output of said FCU instance in response to receiving an overflow signal at an overflow input of said FCU instance (Paragraphs 0020-0021). Please note that and overflow is being interpreted with respect to Paragraph 0065 of Applicant’s specification.
Therefore, it would have been obvious to one of ordinary skill in the art in which said subject matter pertains to, prior to the effective filing date of the claimed invention, use an overflow signal, as taught by Pedersen, in the hierarchical error reporting system of Wang in view of Nautiyal, in order to handle simultaneous errors (Pedersen, Paragraph 0020) and mask a number of errors considered to be tolerable to handle different modes (Pedersen, Paragraph 0032).
With regards to Claim 5, Wang in view of Nautiyal teaches the system of Claim 4 as cited above. Wang in view of Nautiyal further teaches:
… two or more fault input signals having different fault EID values are receiving at the one or more fault inputs of said FCU instance (Wang, Col. 15, Lines 6-60; Col. 16, examples in charts; Fig. 6).
Wang in view of Nautiyal does not explicitly teach:
where each FCU instance is further configured to generate an overflow signal at an overflow output of said FCU instance if …
However, Pedersen teaches:
where each FCU instance is further configured to generate an overflow signal at an overflow output of said FCU instance if two or more fault input signals having different … are receiving at the one or more fault inputs of said FCU instance (Paragraphs 0020-0021).
Therefore, it would have been obvious to one of ordinary skill in the art in which said subject matter pertains to, prior to the effective filing date of the claimed invention, use an overflow signal, as taught by Pedersen, in the hierarchical error reporting system of Wang in view of Nautiyal, in order to handle simultaneous errors (Pedersen, Paragraph 0020) and mask a number of errors considered to be tolerable to handle different modes (Pedersen, Paragraph 0032).
All limitations of Claims 12 and 19 have been addressed in the analysis of Claim 3. Please see the above rejections for further details, including the motivation to combine references in accordance with 35 U.S.C. 103.
All limitations of Claim 15 have been addressed in the analysis of Claim 5. Please see the above rejections for further details, including the motivation to combine references in accordance with 35 U.S.C. 103.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Avizienis (U.S. Publication No. 2007/0067673 A1): teaches a hierarchical configuration for error correction in a System on a Chip
Davis et al. (U.S. Publication No. 2011/0172968 A1): teaches daisy-chained performance modules for processing cores
Ditty et al. (U.S. Publication No. 2023/0036130 A1): teaches a system for forwarding uncorrected errors in a System on a Chip
Hu et al. (U.S. Publication No. 2016/0055052 A1): teaches forwarding uncorrected memory errors
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/G.K.S./Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113