Prosecution Insights
Last updated: April 18, 2026
Application No. 18/979,984

MAINBOARDS FOR SECURITY VERIFICATION, SECURITY VERIFICATION METHODS AND APPARATUSES, AND MEDIA

Non-Final OA §103
Filed
Dec 13, 2024
Examiner
ARYAL, AAYUSH
Art Unit
2435
Tech Center
2400 — Computer Networks
Assignee
Alipay (Hangzhou) Information Technology Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
94%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
88 granted / 103 resolved
+27.4% vs TC avg
Moderate +9% lift
Without
With
+9.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
12 currently pending
Career history
115
Total Applications
across all art units

Statute-Specific Performance

§101
3.6%
-36.4% vs TC avg
§103
57.2%
+17.2% vs TC avg
§102
18.7%
-21.3% vs TC avg
§112
13.6%
-26.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 103 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 06/09/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Allowable Subject Matter Claims 2-6 and 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding Claims 2 and 12, known prior art does not explicitly disclose determine, based on the device identifier carried in the second verification instruction, the another device corresponding to the device identifier; obtain peripheral configuration information from the device; and send the peripheral configuration information to the verification unit based on the second verification instruction. Claims 3-4 and 6 are allowed due to their dependency to Claim 2. Claims 13-14 and 16 are allowed due to their dependency to Claim 12. Regarding Claim 5 and 15, known prior art does not explicitly disclose wherein the channel management unit is a chip that predefines a data transmission standard of each pin, and wherein the channel management unit is configured to: for at least a part of pins, determine an idle time period of the pin based on a data transmission standard of the pin; and transmit the configuration information in the idle time period, wherein the idle time period is a time period not predefined for data transmission by the pin. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1,7,9-11,17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US2011302459) in view of LI (CN105959249). Regarding Claims 1,11 and 20 Hu discloses wherein the mainboard comprises a verification unit and a channel management unit coupled to the verification unit, wherein the verification unit is configured to: (Figure 1 Examiner Note (E.N.) A block diagram of a computing device including a test system is disclosed.) send a verification instruction for a device to be verified to the channel management unit; (Paragraph [0027] and Figure 4 E.N. The writing module writes data to the storage device through the data transmission path. The data are transmitted to the storage device though the selected hard port of the ports, the corresponding serial ports of the serial ports and the corresponding channel of the multiplexer) and receive configuration information of the device from the channel management unit; (Paragraph [0028] and Figure 4 E.N. Data is read from the storage device though the data transmission path) verify the configuration information (Paragraph [0029] The data is read from the storage device through the data transmission path, if the written data is identical to the read data, the hard disk port is working normally, if not the hard disk port is not working normally.) stored by the verification unit; (Paragraph [0033] E.N. The switch module determines whether all the hard disk ports have been selected.) and start the electronic device after it is determined that the device is verified; (Paragraph [0034] E.N. The sending module sends a completed message to the multiplexer to activate the one or more indicators to indicate all the hard disk ports have been tested, and indicate that the hard disk ports on the motherboard work.) and the channel management unit is configured to: determine the device based on the received verification instruction; (Paragraph [0013] and [0017] E.N. The switch system is operable to select a hard disk port to be tested from the group of the ports, and send a port selection message to the multiplexer through the I/O port and the I/O port conversion unit.) obtain the configuration information of the device; and send the configuration information to the verification unit. (Paragraph [0020] and [0028] E.N. The reading module is operable to read data from the storage device through the data transmission path.) Hu does not, but in related art, Ll discloses A mainboard for security verification comprised in an electronic device, (Paragraph [0012] E.N. A server performing verification calculation on a reference value to generate a first verification value) based on verification information Paragraph [0012] E.N. After the first verification value is verified successfully, the management device acquiring status data of an electronic device connected to the management device; the management device performing verification calculations on the status data of the electronic device and the reference value to generate a second verification value) Therefore, it would be obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention to have modified Hu to incorporate the teachings of LI because Hu does not explicitly disclose a mainboard for security verification and verification information which is disclosed by Ll. Incorporating the teachings of Ll to Hu allows for the use of verification information to successfully verify the device/information in a secure manner. Regarding Claim 7 and Claim 17, Hu in view of Ll discloses the mainboard of claim 1 and the method of claim 11. Hu further discloses and power off the electronic device. (Figure 4 E.N. The sending module sends a failure message to the multiplexer to activate the one or more indicators to indicate that the hard disk port is not working normally. One of ordinary skill in the art can determine if the device is not working properly, conditions may be triggered that result in the device to power down.) Hu does not, but in related art, Ll discloses wherein the verification unit is configured to: in response to determining, based on the received configuration information, that verification fails, determine that the electronic device is unreliable; (Paragraph [0047] E.N. If the server fails to verify the second checksum, it indicates that the response message comes from an untrusted device and/or there are security risks. In this case, the server can determine that the management device is in an abnormal state and issue an early warning notification to inform relevant personnel that the management device is experiencing an abnormal situation) Therefore, it would be obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention to have modified Hu to incorporate the teachings of LI because Hu does not explicitly disclose determining that the device is unreliable which is disclosed by Ll. Incorporating the teachings of Ll to Hu allows for the use of verification information to successfully verify the device/information in a secure manner and contact the administrator if the device is not working properly to mitigate the issue. Regarding Claim 9 and 19, Hu in view of Ll discloses the mainboard of claim 1 and the method of claim 11. Hu further discloses wherein the verification unit is configured to send a reset instruction carrying a device identifier to the channel management unit; and the channel management unit is configured to: forward the reset instruction to a device corresponding to the device identifier for restoring the device to an initial state; obtain configuration information of the device after the initial state is restored; and send the configuration information to the verification unit. (Figure 4 and Paragraph [0022-0023] E.N. The hard disk port is tested and the written data is determined if it is identical to the read data, if it is, the hard disk port is working properly and the written data from the storage device is erased (reset/restored)) Regarding Claim 10, Hu in view of Ll discloses the mainboard according to claim 1. Hu further discloses wherein the channel management unit is configured to: after the device is determined, gate a channel connected to the device; and obtain the configuration information of the device through the channel. (Paragraph [0013] E.N. The I/O port conversion unit converts the message into a control signal for controlling the multiplexer. The control signal may be an Inter-integrated Circuit (I<2>C) signal or a Serial Peripheral Interface (SPI) signal. The multiplexer switches on a channel corresponding to a port name of the hard disk port according to the port selection.) Claim(s) 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US2011302459) in view of LI (CN105959249) and in further view of Rahn. Regarding Claims 8 and 18, Hu in view of Ll discloses the mainboard according to claim 1 and the method of claim 11. Hu and Ll do not, but in related art, Rahn discloses wherein the electronic device comprises a control unit connected to the channel management unit, and wherein the verification unit is configured to: send, to the channel management unit, a suspend instruction to pause starting of the electronic device; (Col 6 lines 18-31 E.N. If one or more of the authentication/attestation procedures fails to complete successfully, the software operating on the device may suspend normal operation of the device and/or notify an administrator of the device of the failure.) and send, to the channel management unit, a start instruction to continue to start the electronic device after it is determined that the device is verified; (Col 6 lines 18-31 E.N. If authentication/attestation is successful using at least some of or all of the procedures described above, the software operating on the device may proceed at block 480 with operating the device normally (e.g., fully performing network switching/routing functions) and the channel management unit is configured to: connect to the control unit based on the received suspend instruction; send the suspend instruction to the control unit, so as to pause starting of an operating system pre-deployed in the control unit; (Col 6 lines 18-31 E.N. If one or more of the authentication/attestation procedures fails to complete successfully, the software operating on the device may suspend normal operation of the device and/or notify an administrator of the device of the failure. One of ordinary skill in the art can determine, some form of instruction is sent to a control unit to suspend normal operation.) and send the received start instruction to the control unit, so as to start the operating system in the control unit. (Col 6 lines 18-31 E.N. If authentication/attestation is successful using at least some of or all of the procedures described above, the software operating on the device may proceed at block 480 with operating the device normally (e.g., fully performing network switching/routing functions) Therefore, it would be obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention to have modified Hu in view of Ll to incorporate the teachings of Rahn because Hu and Ll do not explicitly disclose suspending and starting the device which is taught by Rahn. Incorporating the teachings of Rahn to Hu and Ll allows for the device to be suspended if there is an issue allowing for the mitigation of the said issue prior to starting the device once the issue has been fixed. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to AAYUSH ARYAL whose telephone number is (571)272-2838. The examiner can normally be reached 8:00 a.m. - 5:30 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Mehrmanesh can be reached at (571) 270-3351. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AAYUSH ARYAL/Examiner, Art Unit 2435 /AMIR MEHRMANESH/Supervisory Patent Examiner, Art Unit 2435
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Prosecution Timeline

Dec 13, 2024
Application Filed
Apr 04, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
94%
With Interview (+9.0%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 103 resolved cases by this examiner. Grant probability derived from career allow rate.

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