DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to amendments and remarks filed July 23, 2026. Claims 2-19 are currently pending.
Response to Arguments
Applicant's arguments filed July 23, 2026 have been fully considered but they are not persuasive.
In regards to the Applicant’s argument that the rationale to combine is insufficient and is only a generalized benefit (Applicant’s arguments, page 9), Examiner respectfully disagrees. In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, just because the rationale leads to a generalized benefit does not mean there is no benefit. For example, Liu leaves the specific structure of the pixels open ended, there is not specific structure, just as long as there is a photodetector, such as a photodiode, outputting a signal that is dependent on the light captured at said pixel (paragraph 36-38). The only constraint for the pixels being the pixels are arrayed in separate pixel/photodetector layer from a processing circuitry layer, where the different layers are stacked allowing for smaller area coverage so that the entire sensor assembly is more compact to fit within smaller devices, such as a headset (see fig. 1). To improve pixel output, one of ordinary skill would understand to look into various pixel structures to increase gain, SNR, dynamic range and resolution. One such solution is a pixel architecture seen in Hseih. Not only is the pixel structure that is provided meant to improve gain, SNR, dynamic range and resolution, it is also part of a stacked structure with processing circuitry, which allows for smaller overall size of a camera/sensor assembly (Hseih, paragraph 26). Adding the pixel structure of Hseih in the pixels of Liu would not hinder or destroy the camera/sensor assembly of Liu. The pixel structure of Hseih would improve the outputted pixel signal of Liu, which is then output to the processing layers of Liu. For these reasons the combination of Liu with Hseih remains proper and the rejection of claims 2-15 remains proper. Claims 16-19 are newly added and will be further considered below.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “wherein the first photodiode is disposed on the first substrate and the first transistor, the first capacitor, the second transistor, and the amplification transistor are disposed on the second substrate” in claim 19 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 19 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In regards to claim 19, the limitation “wherein the first photodiode is disposed on the first substrate and the first transistor, the first capacitor, the second transistor, and the amplification transistor are disposed on the second substrate” is not described in the specification or shown in the drawings. First, claim 1 states the second substrate includes a memory array, which according to the specification is on the second substrate (102) as see in figure 2 of the Applicant’s specification. The second substrate also includes a pixel signal processing circuit (13), but this is not the first transistor, the first capacitor, the second transistor, and the amplification transistor seen in Applicant’s figure 5. The processing circuit according to paragraphs 30 includes a correlated double sampling circuit and an analog to digital circuit. The pixel signal from the pixel that includes the photodiode, the first transistor, the first capacitor, the second transistor, and the amplification transistor is sent via wiring (56) to the signal processing circuitry (13) (Applicant’s specification paragraphs 65-68). This teaches away from the transistor circuitry and capacitor of the pixel from being on the second substrate. The entire pixel is on the first substrate where the pixel array is located. There is no other mention of the claim limitation where the first transistor, the first capacitor, the second transistor, and the amplification transistor are disposed on the second substrate. Since, the claim limitation is not taught in the specification or drawing, this claim is considered new matter.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 12249611 in view of Hseih et al. (US 20160165159).
In regards to claim 2, 12249611 teaches an imaging device (claim 1) comprising: a first substrate on which a pixel array that outputs a pixel signal obtained by photoelectrically converting incident light in a first direction is arranged (claim 1, lines 2 4); and a second substrate on which a memory array that outputs a convolution signal indicating a result of a product-sum operation of an input signal based on the pixel signal in a second direction is arranged (claim 1, lines 5-8), wherein the first substrate and the second substrate at least partially overlap each other, and the pixel array comprises a plurality of pixels (claim 1, lines 1-10), but does not specifically teach the at least one of the pixels comprising a first photodiode configured to generate a first charge by photoelectrically converting a first incident light; a first transistor coupled to the first photodiode and configured to transfer the first charge generated by the first photodiode; a first capacitor coupled to the first transistor and configured to hold the first charge transferred from the first transistor; a second transistor coupled to the first capacitor and configured to transfer the first charge held by the first capacitor; and an amplification transistor coupled to the second transistor and configured to output an amplified signal as the pixel signal based on the first charge transferred from the first capacitor. Hseih teaches a pixel array comprises a plurality of pixels (paragraph 32), at least one of the pixels (fig. 1a) comprising a first photodiode (PD1) configured to generate a first charge by photoelectrically converting a first incident light (paragraph 37 and 38); a first transistor (TG1) coupled to the first photodiode (PD1) and configured to transfer the first charge generated by the first photodiode (PD1) (paragraph 37-39); a first capacitor (CS1) coupled to the first transistor (TG1) and configured to hold the first charge transferred from the first transistor (TG1) (paragraph 37-39); a second transistor (TS1) coupled to the first capacitor (CS1) and configured to transfer the first charge held by the first capacitor (CS1) (paragraph 37-39); and an amplification transistor (SF amp) coupled to the second transistor (TS1) and configured to output an amplified signal as the pixel signal based on the first charge transferred from the first capacitor (CS1) (paragraph 42, fig. 1a). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the pixel of 12249611 include a photodiode, transistors and capacitor arranged similar to Hseih in order to output a pixel signal with improved signal to noise and gain providing for higher quality image capture.
In regards to claim 3, 12249611 as modified by Hseih teaches The imaging device according to claim 2, wherein the at least one the pixels further comprises: a second photodiode configured to generate a second charge by photoelectrically converting a second incident light (Hseih, PD2); a third transistor coupled to the second photodiode and configure to transfer the second charge generated by the second photodiode (Hseih, TG2); a second capacitor coupled to the third transistor and configured to hold the second charge transferred from the third transistor (Hseih, CS2); and a fourth transistor coupled to the second capacitor and configured to transfer the second charge held by the second capacitor to the amplification transistor (Hseih, TS2, fig. 1a, paragraphs 37-42).
In regards to claims 4-19 are covered by or are obvious variants of the pixel structure in Hseih, see fig. 1a, paragraphs 37-44.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 20190035154) in view of Hseih et al. (US 20160165159).
Re claim 2: Liu teaches an imaging device (paragraph 4, fig. 3-5) comprising: a first substrate (305/405) on which a pixel array unit (310/415, paragraph 38) that outputs a pixel signal obtained by photoelectrically converting incident light in a first direction is arranged (see fig. 3, 4 and 5, the output of the pixel signals is in the y direction down to the MUX); and a second substrate (325/500) on which a memory array (Gn, n, paragraph 52) that outputs a convolution signal (515) (paragraph 55) indicating a result of a product-sum operation of an input signal (510) based on the pixel signal in a second direction is arranged (fig. 3, 4 and 5, the output convolution signal is output in the y direction parallel to the direction of the output pixel signal, since the first 305/405 and second 325/500 substrates are stacked), wherein the first substrate (305/405) and the second substrate (325/500) at least partially overlap each other (see fig. 3, paragraph 8-11) and the pixel array comprises a plurality of pixels (310/415, paragraph 38), at least one of the pixels comprising a first photodiode configured to generate a first charge by photoelectrically converting a first incident light (paragraph 38), but does not specifically teach a first transistor coupled to the first photodiode and configured to transfer the first charge generated by the first photodiode; a first capacitor coupled to the first transistor and configured to hold the first charge transferred from the first transistor; a second transistor coupled to the first capacitor and configured to transfer the first charge held by the first capacitor; and an amplification transistor coupled to the second transistor and configured to output an amplified signal as the pixel signal based on the first charge transferred from the first capacitor. Hseih teaches a pixel array comprises a plurality of pixels (paragraph 32), at least one of the pixels (fig. 1a) comprising a first photodiode (PD1) configured to generate a first charge by photoelectrically converting a first incident light (paragraph 37 and 38); a first transistor (TG1) coupled to the first photodiode (PD1) and configured to transfer the first charge generated by the first photodiode (PD1) (paragraph 37-39); a first capacitor (CS1) coupled to the first transistor (TG1) and configured to hold the first charge transferred from the first transistor (TG1) (paragraph 37-39); a second transistor (TS1) coupled to the first capacitor (CS1) and configured to transfer the first charge held by the first capacitor (CS1) (paragraph 37-39); and an amplification transistor (SF amp) coupled to the second transistor (TS1) and configured to output an amplified signal as the pixel signal based on the first charge transferred from the first capacitor (CS1) (paragraph 42, fig. 1a). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the pixel of Liu include the photodiode, transistors and capacitor arranged similar to Hseih in order to output a pixel signal with improved signal to noise and gain providing for higher quality image capture.
Re claim 3: Liu as modified by Hseih teaches the imaging device, wherein the at least one the pixels further comprises: a second photodiode (Hsieh, PD2) configured to generate a second charge by photoelectrically converting a second incident light (Hsieh, paragraph 37 and 38); a third transistor (Hseih, TG2) coupled to the second photodiode (Hsieh, PD2) and configure to transfer the second charge generated by the second photodiode (Hsieh, PD2, fig. 1a, paragraph 37 and 38); a second capacitor (Hseih, CS2) coupled to the third transistor (Hseih, TG2) and configured to hold the second charge transferred from the third transistor (Hseih, TG2, paragraph 37-39); and a fourth transistor (Hseih, TS2) coupled to the second capacitor (Hseih, CS2) and configured to transfer the second charge held by the second capacitor (Hseih, CS2) to the amplification transistor (Hseih, SF amp, paragraph 42, fig. 1a).
Re claim 4: Liu as modified by Hseih teaches the imaging device, further comprising: a reset transistor (Hseih, RST) coupled to the second transistor (Hseih, TS1) and the fourth transistor (Hseih, TS2, fig. 1a).
Re claim 5: Liu as modified by Hseih teaches the imaging device, further comprising: a reset transistor (Hseih, RST) coupled to the second transistor (Hseih, TS1, fig. 1a).
Re claim 6: Liu as modified by Hseih teaches the imaging device, wherein the reset transistor (Hseih, RST) includes a gate terminal, a first terminal and a second terminal, the first terminal being coupled to a gate terminal of the amplification transistor (Hseih, SFamp, see fig. 1a, first terminal of RST connected to gate of SFamp and FD).
Re claim 7: Liu as modified by Hseih teaches the imaging device, wherein the second terminal of the reset transistor (Hseih, RST) is coupled to a first terminal of the amplification transistor (Hseih, SFamp) and a power supply voltage (Hseih, Vdd, see fig. 1a, the second terminal of RST connected to Vdd and first terminal of SFamp).
Re claim 8: Liu as modified by Hseih teaches the imaging device, further comprising: a selection transistor (Hseih, SEL) coupled to the amplification transistor (Hseih, SFamp, see fig. 1a).
Re claim 9: Liu as modified by Hseih teaches an electronic device comprising the imaging device of claim 2 (Hseih, fig. 1a and 8, paragraph 2, Liu, fig. 1, paragraph 2 and 3).
Re claim 10: Liu as modified by Hseih teaches the electronic device, wherein the at least one the pixels further comprises: a second photodiode (Hsieh, PD2) configured to generate a second charge by photoelectrically converting a second incident light (Hsieh, paragraph 37 and 38); a third transistor (Hseih, TG2) coupled to the second photodiode (Hsieh, PD2) and configure to transfer the second charge generated by the second photodiode (Hsieh, PD2, fig. 1a, paragraph 37 and 38); a second capacitor (Hseih, CS2) coupled to the third transistor (Hseih, TG2) and configured to hold the second charge transferred from the third transistor (Hseih, TG2, paragraph 37-39); and a fourth transistor (Hseih, TS2) coupled to the second capacitor (Hseih, CS2) and configured to transfer the second charge held by the second capacitor (Hseih, CS2) to the amplification transistor (Hseih, SFamp, paragraph 42, fig. 1a).
Re claim 11: Liu as modified by Hseih teaches the electronic device, further comprising: a reset transistor (Hseih, RST) coupled to the second transistor (Hseih, TS1) and the fourth transistor (Hseih, TS2, fig. 1a).
Re claim 12: Liu as modified by Hseih teaches the electronic device, further comprising: a reset transistor (Hseih, RST) coupled to the second transistor (Hseih, TS1, fig. 1a).
Re claim 13: Liu as modified by Hseih teaches the electronic device, wherein the reset transistor (Hseih, RST) includes a gate terminal, a first terminal and a second terminal, the first terminal being coupled to a gate terminal of the amplification transistor (Hseih, SFamp, see fig. 1a, first terminal of RST connected to gate of SFamp and FD).
Re claim 14: Liu as modified by Hseih teaches the electronic device, wherein the second terminal of the reset transistor (Hseih, RST) is coupled to a first terminal of the amplification transistor (Hseih, SFamp) and a power supply voltage (Hseih, Vdd, see fig. 1a, the second terminal of RST connected to Vdd and first terminal of SFamp).
Re claim 15: Liu as modified by Hseih teaches the electronic device, further comprising: a selection transistor (Hseih, SEL) coupled to the amplification transistor (Hseih, SFamp, see fig. 1a).
Re claim 16: Liu as modified by Hseih teaches the imaging device, wherein the gate terminal of the amplification transistor (Hseih, SFamp) and the first terminal of the reset transistor (Hseih, RST) are connected to a common floating diffusion node (Hseih, FD, see fig. 1a).
Re claim 17: Liu as modified by Hseih teaches the imaging device, wherein the first capacitor (Hseih, CS1) is coupled to the common floating diffusion node (Hseih, FD) through the second transistor (Hseih, TS1, see fig. 1a).
Re claim 18: Liu as modified by Hseih teaches the imaging device, wherein the reset transistor (Hseih, RST) is configured to reset a gate node of the amplification transistor (Hseih, SF amp) and to reset the first capacitor (Hseih, CS1, paragraph 41).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 20190035154) as modified by Hseih et al. (US 20160165159) as applied to claim 2 above, and further in view of Ikeda et al. (US 20180039882).
Re claim 19: Liu as modified by Hseih teaches the imaging device, wherein the first photodiode (Hseih, PD1) is disposed on the first substrate (Hseih, 410) and the first transistor (Hseih, TG1), the first capacitor (Hseih, CS1), the second transistor (Hseih, TS1) are disposed on the first substrate (Hseih, 410), and the amplification transistor (Hseih, SFamp) are disposed on the substrate (Hseih, 420), but does not specifically teach the first transistor, the first capacitor, the second transistor are disposed on the second substrate. Ikeda teaches wherein a first photodiode (PD) a pixel is disposed on a first substrate (1100) and a plurality of transistors and a capacitor of the pixel is disposed on a second substrate (1200) (fig. 9, paragraph 197-200). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to place all of the pixel circuitry except the photodiode on a separate substrate similar to Ikeda with the device of Liu as modified by Hseih in order to increase the amount of coverage by the photodiode without interference from the other circuitry increasing the amount of light captured by the photodiode.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER D BENNETT whose telephone number is (571)270-3419. The examiner can normally be reached 9AM-6PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Georgia Epps can be reached at 571-272-2328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JENNIFER D BENNETT/Examiner, Art Unit 2878
Prosecution Insights