Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1, 3, 5, 7, 9, 11, 14, 16 and 18 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Gomm (US 2007/0030754).
Regarding claim 1, Gomm discloses a semiconductor device (Paragraphs 0004, 0005 and 0054 disclose the device comprises integrated circuits and semiconductor devices.) comprising:
a first digital control delay (DCD) circuit configured to delay an integer output divider (IOD) signal to generate a first delayed IOD signal (Figure 6: the output of the divide by 2 block 46 provides an input to the first delay line 12. The first delay line 12 outputs a signal on line 44 to the second delay line 14.);
a second DCD circuit configured to delay the first delayed IOD signal to generate a second delayed IOD signal (Figure 6: The second delay line 14 receives an output from the first delay line 12.);
an edge sampler configured to sample an edge of the second delayed IOD signal (Figure 6. The phase detector 48 receives one or more signals from the second delay line 14 and the divide by 2 block 46 and detects or samples the edges of the received signal. Figure 4 shows the rising and falling edges of the detected and sampled signals A and B. The phase detector 46 generates a signal indicating the results of the comparison.); and
a controller configured to calibrate the first DCD circuit based on the edge sampled from the second delayed IOD signal (Figure 6. The phase detector 48 outputs signal 24 to control the delays in the first delay line 12 and the second delay line 14.).
Regarding claim 3, Gomm discloses wherein the edge is one of a rising edge and a falling edge of the second delayed IOD signal (Figures 4 and 5: the output of the second delay line 14 is signal B. the rising and falling edges of the second delay line 14 is shown in figures 4 and 5.).
Regarding claim 5, Gomm discloses wherein the controller is configured to calibrate the first DCD circuit periodically (Figure 6: the phase detector provides an output on line 24 to the first and second delay lines. Paragraph 0007: control signal 24 controls the delays imparted on delay lines 12 and 14 so as to ensure the delay between the loop delay and the feedback signal is exactly one cycle. This control is conducted periodically as determined by the result of the comparison.).
Regarding claim 7, Gomm discloses a system (Figure 6) comprising:
a divider configured to divide an input clock signal to generate an integer output divider (IOD) signal (Figure 6: divide by 2 clock 46 divides the clock in signal and generates an integer output divider signal.);
a circuit (Figure 6) comprising:
a first digital control delay (DCD) circuit configured to delay an integer output divider (IOD) signal to generate a first delayed IOD signal (Figure 6: the output of the divide by 2 block 46 provides an input to the first delay line 12. The first delay line 12 outputs a signal on line 44 to the second delay line 14.);
a second DCD circuit configured to delay the first delayed IOD signal to generate a second delayed IOD signal (Figure 6: The second delay line 14 receives an output from the first delay line 12.);
an edge sampler configured to compare an edge of the second delayed IOD signal with an edge of the input clock signal (Figure 6. The phase detector 48 receives one or more signals from the second delay line 14 and input signal through the divide by 2 block 46 and detects or samples the edges of the received signal. Figure 4 shows the rising and falling edges of the detected and sampled signals A and B. The phase detector 46 generates a signal indicating the results of the comparison.); and
a controller configured to calibrate the first DCD circuit based on a result of the comparison between the edge of the second delayed IOD signal with the edge of the input clock signal (Figure 6. The phase detector 48 outputs signal 24 to control the delays in the first delay line 12 and the second delay line 14.).
Regarding claim 9, Gomm discloses wherein the edge is one of a rising edge and a falling edge (Figures 4 and 5: the output of the second delay line 14 is signal B. the rising and falling edges of the second delay line 14 is shown in figures 4 and 5.).
Regarding claim 11, Gomm discloses wherein the controller is configured to calibrate the first DCD circuit periodically (Figure 6: the phase detector provides an output on line 24 to the first and second delay lines. Paragraph 0007: control signal 24 controls the delays imparted on delay lines 12 and 14 so as to ensure the delay between the loop delay and the feedback signal is exactly one cycle. This control is conducted periodically as determined by the result of the comparison.).
Regarding claim 14, Gomm discloses a method comprising:
dividing an input clock signal to generate an integer output divider (IOD) signal (Figure 6: the output of the divide by 2 block 46 provides an input to the first delay line 12. The first delay line 12 outputs a signal on line 44 to the second delay line 14.);
delaying the IOD signal to generate a first delayed IOD signal; delaying the first delayed IOD signal to generate a second delayed IOD signal (Figure 6: The second delay line 14 receives an output from the first delay line 12.);
comparing an edge of the second delayed IOD signal with an edge of the input clock signal (Figure 6. The phase detector 48 receives one or more signals from the second delay line 14 and input signal through the divide by 2 block 46 and detects or samples the edges of the received signal. Figure 4 shows the rising and falling edges of the detected and sampled signals A and B. The phase detector 46 generates a signal indicating the results of the comparison.); and
calibrating a digital control delay (DCD) circuit that generated the first delayed IOD signal , wherein the calibration is based on a result of the comparison between the edge of the second delayed IOD signal with the edge of the input clock signal (Figure 6. The phase detector 48 outputs signal 24 to control the delays in the first delay line 12 and the second delay line 14.).
Regarding claim 16, Gomm discloses wherein the edge is one of a rising edge and a falling edge (Figures 4 and 5: the output of the second delay line 14 is signal B. the rising and falling edges of the second delay line 14 is shown in figures 4 and 5.).
Regarding claim 18, Gomm discloses wherein calibrating the DCD circuit is performed periodically (Figure 6: the phase detector provides an output on line 24 to the first and second delay lines. Paragraph 0007: control signal 24 controls the delays imparted on delay lines 12 and 14 so as to ensure the delay between the loop delay and the feedback signal is exactly one cycle. This control is conducted periodically as determined by the result of the comparison.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 4, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Gomm (US 2007/0030754) in view of Lin (US 11,476,776).
Regarding claims 4, 10 and 17, Gomm discloses the device, system and method as stated above. Gomm does not disclose the controller is configured to: tune a capacitance of the second DCD circuit; and supply a bias to tune a current source of the second DCD circuit.
Lin discloses a device comprising a voltage controlled delay buffer comprising a tunable current source configured to charge a capacitor in accordance with an input signal, the capacitor is charged by the tunable current source when the input signal is high, a current of the tunable current source is controlled by a bias voltage that serves as a voltage signal that controls the delay as stated in column 1, lines 46-56. This delay control will allow the desired delay to be implemented in the device. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lin into delay lines of the device, system and method of Gomm. By implementing known methods of implementing and adjusting delays of the delay lines, the cost and complexity of the device, system and method will be reduced, improving the efficiency of device, system or method.
Allowable Subject Matter
3. The following is a statement of reasons for the indication of allowable subject matter: None of the cited references discloses the second DCD circuit operates under a zero delay mode and under a one delay mode as stated in claims 2, 6, 8, 9, 12, 13, 15, 19 and 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN M. BURD whose telephone number is (571)272-3008. The examiner can normally be reached 9:30 - 5:00.
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/KEVIN M BURD/Primary Examiner, Art Unit 2632 7/30/2026
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