Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on May 29, 2026.
Remarks
The Office has cited particular columns, line numbers, paragraph numbers, references, or figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 9 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ghosh et al. (US 2023/0170855 A1, hereinafter referred to as Ghosh).
Regarding claim 1, Ghosh discloses a chip (Figs. 1, 2), comprising: a first modulator (104, 210, paras 0030, 0037) configured to receive a first internal signal (203), and convert the first internal signal into a first output signal including a first pattern (LP45, Fig. 2); a second modulator (104, 214, paras 0030, 0037) configured to receive a second internal signal (207), and convert the second internal signal into a second output signal including a second pattern (LN45) distinct from the first pattern; an observation pad (TXO, iPA); and a merge circuit (108, 110, 112) coupled to the observation pad, wherein the merge circuit is configured to merge the first output signal and the second output signal into a merged output signal (TXO, iPA, Fig. 5), and output the merged output signal to the observation pad, wherein the merged output signal includes the first pattern and the second pattern, and the first pattern and the second pattern are spaced apart in the merged output signal (see iPA in Fig. 5).
Regarding claim 2, Ghosh discloses the chip of claim 1, wherein the first internal signal comprises a first enable signal (HS_EN) for selectively enabling a first circuit (M1, Fig. 3) on the chip.
Regarding claim 3, Ghosh discloses the chip of claim 2, wherein the second internal signal comprises a second enable signal (HS_EN) for selectively enabling a second circuit (M4, Fig. 3) on the chip.
Regarding claim 4, Ghosh discloses the chip of claim 1, further comprising a third modulator (104, 212, paras 0030, 0037) configured to receive a third internal signal (205, para 0035), and convert the third internal signal into a third output signal including a third pattern (L0) distinct from the first pattern and the second pattern, wherein the merge circuit is configured to merge the first output signal, the second output signal, and the third output signal into the merged output signal (TXO, iPA, Fig. 5).
Regarding claim 6, Ghosh discloses the chip of claim 1, wherein the first pattern comprises a first sequence of ones and zeros (see MP25DC in Fig. 5), and the second pattern comprises a second sequence of ones and zeros (see MN25DC in Fig. 5) distinct from the first sequence of ones and zeros.
Regarding claim 9, Ghosh discloses the chip of claim 1, wherein the merge circuit comprises an OR gate (216 in Fig. 2).
Method claim 20 is essentially the same in scope as claim 1 and is rejected similarly.
Allowable Subject Matter
Claims 5, 7, and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Swoboda (US 5828824 A) discloses a method for debugging an integrated circuit using extended operating modes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL D CHANG whose telephone number is (571)272-1801. The examiner can normally be reached M-F 8-5 EST.
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/DANIEL D CHANG/ Primary Examiner, Art Unit 2845
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