DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 9-12 is/are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Lin et al. U.S. Patent No. 11,081,038 (hereinafter Lin).
Consider claim 1, Lin teaches a display device, comprising: a timing controller configured to output image data and command data including a plurality of pseudo bits (Figure 1, 300; Column 2, lines 53-60; column 3, lines 14-29, MSB); a display panel including a plurality of pixels connected respectively to a plurality of data lines (Figure 1, 20 and Dm); and a data driver configured to generate a data voltage based on the image data and to apply the data voltage to at least one data line among the plurality of data lines (Figure 1, 100; Column 2, lines 53-60), wherein the data driver includes: a pseudo shift register configured to generate a clock for latching the image data and the command data (Figure 2, 110; column 3, lines 4-13); a latch configured to maintain and output a per-frame image data on an at least one channel basis (Figure 2, 120; column 3, lines 7-12); a pseudo latch configured to store the pseudo bits of the image data and the command data (Figure 2, 130, Figure 3, 131-132; column 3, lines 20-23, the second latch circuit 130 further detects a most significant bit (MSB) of a sampled signal corresponding to a current data line Dk, and detects whether the current data line Dk is within a specified range; column 3, lines 52-58, the MSB latch unit 1312 latches the sampled signal Sample(k-1) of the previous data line D(k-1) and outputs the latched previous sampled signal Sample(k-1) of the current data line D(k-1) to the MSB comparison unit 1314 based on the second clock signal MCLK, the reset signal Reset, and the received the sampled signal Sample(k) of the current data line Dk); and an output buffer configured to output the data voltage to the at least one data line (Figure 2, 160 and D1-Dm).
Consider claim 2, Lin teaches all the limitations of claim 1. In addition, Lin teaches wherein the pseudo latch is disposed at an end of the pseudo shift register (Figure 2, 130 and 110).
Consider claim 3 , Lin teaches all the limitations of claim 2. In addition, Lin teaches wherein the pseudo bits of the image data and the command data are disposed at a start end of one transmission unit (Figures 3-5, MSB).
Consider claim 4, Lin teaches all the limitations of claim 1. In addition, Lin teaches wherein the pseudo latch is disposed at a start end of the pseudo shift register (Figure 2, 130 and 110).
Consider claim 9, Lin teaches a data driver, comprising (Figure 1, 100): a pseudo shift register configured to generate a clock for latching image data and command data that include a plurality of pseudo bits (Figure 2, 110; column 3, lines 4-13; column 3, lines 14-29, MSB); a latch configured to maintain and output a per-frame image data on an at least one channel basis (Figure 2, 120; column 3, lines 7-12); a pseudo latch configured to store the pseudo bits of the image data and the command data (Figure 2, 130, Figure 3, 131-132; column 3, lines 20-23, the second latch circuit 130 further detects a most significant bit (MSB) of a sampled signal corresponding to a current data line Dk, and detects whether the current data line Dk is within a specified range; column 3, lines 52-58, the MSB latch unit 1312 latches the sampled signal Sample(k-1) of the previous data line D(k-1) and outputs the latched previous sampled signal Sample(k-1) of the current data line D(k-1) to the MSB comparison unit 1314 based on the second clock signal MCLK, the reset signal Reset, and the received the sampled signal Sample(k) of the current data line Dk); a level shifter configured to receive the image data from the latch (Figure 2, 140); a switch array configured to generate a data voltage from the image data (Figure 2, DAC circuit); and an output buffer configured to output the data voltage (Figure 2, 160 and D1-Dm).
Consider claim 10, it includes the limitations of claim 2 and thus it is rejected by the same reasoning.
Consider claim 11, it includes the limitations of claim 3 and thus it is rejected by the same reasoning.
Consider claim 12, it includes the limitations of claim 4 and thus it is rejected by the same reasoning.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 4 above, and further in view of Park U.S. Patent Publication No. 2008/0111772 (hereinafter Park).
Consider claim 5, Lin teaches all the limitations of claim 4. In addition, Lin teaches wherein the pseudo bits of the image data and the command data are disposed in one transmission unit (Figures 4-5, see bits).
Lin does not appear to specifically disclose bits at an end of one transmission unit.
However, in a related field of endeavor, Park teaches a data driver in figure 4 and further teaches bits at an end of one transmission unit (abstract teaches employing upper bits and lower bits).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide bits at an end as taught by Park with the benefit that a second data processing unit should be adapted to output a second voltage employing lower bits of the digital data signal or LSB as mentioned in abstract and shown in figure 4.
Consider claim 13, it includes the limitations of claim 5 and thus it is rejected by the same reasoning.
Allowable Subject Matter
Claims 6-8, 14-15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: Prior art does not appear to disclose the limitations of claims 6 and 14 in combination of the limitations of the base claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621