DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 29 is objected to because of the following informalities: In line 2 the claim recites “any one of Claim 1”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites several frequency ranges described as being equal to or greater than said value. However, the bounds of these limitations cannot be ascertained as no upper limit is provided. Therefore, the limitation as claimed would comprise any frequency approaching infinity.
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-13, 15-22, 24, 28-30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pance[1] (US 2021/0013613 published Jan. 14, 2021).
Claim 1: Pance[1] discloses An electromagnetic, EM, device configured to be operational at a defined center frequency, f, having a free space wavelength, λ, the EM device comprising:
an integrated circuit, IC, chip (para 0198, 0217, 0244, 0267 disclosing disposition of the DRA array on a circuit board); and
a DRA subarray integrally arranged with and disposed on the IC chip (fig 39A, 39B, para 0189);
the DRA subarray comprising a plurality of DRAs, that can resonate at the same frequency, f (para 0084, 0116, 0199), defining a unit cell having an overall footprint of equal to or less than λ /2 in both x and y directions of an orthogonal x-y-z coordinate system, as observed in a plan view of the EM device, where the z-direction is a direction of vertical extension of each DRA of the plurality of DRAs (fig 4A, 39A, 39B, para 0189, 0202)
Claim 2: Pance[1] discloses f is equal to or greater than 50 GHz, alternatively equal to or greater than 60 GHz, further alternatively equal to or greater than 77 GHz, further alternatively equal to or greater than 100 GHz, and equal to or less than 1000 GHz (para 0084, 0116, 0186, 0199)
Claim 3: Pance[1] discloses the DRA subarray is a monolithic construct (para 0189)
Claim 5: Pance[1] discloses the DRA subarray is integrally formed with the IC chip (para 0198, 0217, 0244, 0267 disclosing disposition of the DRA array on a circuit board);
Claim 6: Pance[1] discloses the IC chip comprises a substrate of dielectric material having a first dielectric constant, Dk, and the plurality of DRAs comprise a dielectric material having a second Dk (para 0100, 0102, 0110, 0112, 0120, 0290-0292)
Claim 7: Pance[1] discloses the second Dk is the same as the first Dk (para 0100, 0102, 0110, 0112, 0120, 0290-0292)
Claim 8: Pance[1] discloses the first and second Dk materials each comprise any of: Silicon (Si); Germanium (Ge); Silicon-Germanium (SiGe); Silicon-Carbide (SiC); Gallium Nitride (GaN); or Gallium Arsenide (GaAs) (para 0245)
Claim 9: Pance[1] discloses the dielectric material of the plurality of DRAs is the same as the dielectric material of the substrate of the IC chip (para 0100, 0102, 0110, 0112, 0120, 0290-0292)
Claim 10: Pance[1] discloses each DRA of the plurality of DRAs has a same 3D shape and size (fig 39A, 39B, para 0083, 0189);
Claim 11: Pance[1] discloses the 3D shape of each DRA has a proximal end proximate the IC chip, and an opposing distal end at a distance from the IC chip, the 3D shape tapering inward from the proximal end to the distal end to form and define non-DRA space between each adjacent DRA of the plurality of DRAs (fig 39A, 39B, para 0181, 0189)
Claim 12: Pance[1] discloses the inwardly tapered 3D shape has a first effective Dk value at the proximal end, and a second effective Dk value at the distal end that is less than the first effective Dk value; wherein the respective effective Dk value is defined by the Dk value associated with incremental and uniform 3D cross sectional slices in the z-direction of a non-tapered envelope that bounds both the 3D shape of the respective DRA and the associated portion of non-DRA space about the respective DRA; wherein a thickness h of the 3D cross sectional slices in the z-direction is equal to or less than 10% of an overall height H of the respective DRA (3100’) in the z-direction (para 0083, 0085, 0119, 0120, 0200-0206, 0213)
Claim 13: Pance[1] discloses the first effective Dk value is equal to or greater than 12 and equal to or less than 16, and the second effective Dk value is equal to or greater than 1 and equal to or less than 5 (para 0085, 0100, 0112)
Claim 15: Pance[1] discloses the 3D shape of each DRA has overall outside footprint dimensions, a and b, at the proximal end, and an overall height, H, from the proximal end to the distal end; and H is greater than a, or H is greater than b; alternatively, H is greater than a, and H is greater than b. (para 0083, 0085, 0119, 0120, 0200-0206, 0213)
Claim 16: Pance[1] discloses H is equal to or greater than two times a, or H is equal to or greater than two times b; alternatively, H is equal to or greater than two times a, and H is equal to or greater than two times b. (para 0083, 0085, 0119, 0120, 0200-0206, 0213)
Claim 17: Pance[1] discloses the 3D shape of each DRA has a faceted surface that faces another faceted surface of an adjacent one of the plurality of DRAs (fig 39A, 39B, para 0189);
Claim 18: Pance[1] discloses the DRA subarray is structurally configured to guide an E-field, when present in the EM device, in the non-DRA space between each DRA of the plurality of DRAs (para 0208-0211)
Claim 19: Pance[1] discloses a direction of EM radiation, when present in the EM device, is directed from the proximal end of each DRA to the distal end of each DRA (para 0208-0211)
Claim 20: Pance[1] discloses the unit cell is at least a 2x2 array of the plurality of DRAs; alternatively, the unit cell is at least a 3x3 array of the plurality of DRAs (fig 39A, 39B, para 0189);
Claim 21: Pance[1] discloses a waveguide disposed between, and configured to be in EM communication with, the IC chip and the DRA subarray (para 0083, 0085, 0100)
Claim 22: Pance[1] discloses a ground plane disposed between, and configured to be in EM communication with, the waveguide and the DRA subarray, the ground plane having a plurality of slotted apertures arranged in a one-to-one correspondence with a respective one of the plurality of DRAs (para 0120)
Claim 24: Pance[1] discloses the EM device forms a unitary DRA-subarray-on-chip construct (para 0198, 0217, 0244, 0267 disclosing disposition of the DRA array on a circuit board);
Claim 28: Pance[1] discloses the device is fabricated by the process of the following processes: (1) additive manufacturing; (2) high-resolution 3D printing; (3) ultrahigh-resolution 3D printing; (4) femtosecond laser-induced 3D printing based on two-photon polymerization (TTP); (5) semiconductor device fabrication; (6) laser milling (para 0083)
Claim 29: Pance[1] discloses A fabrication of an electromagnetic, EM, device (1000) according to any one of Claim 1, produced by the process of the following processes: (1) additive manufacturing; (2) high-resolution 3D printing; (3) ultrahigh-resolution 3D printing; (4) femtosecond laser-induced 3D printing based on two-photon polymerization (TTP); (5) semiconductor device fabrication; (6) laser milling (para 0083)
Claim 30: Pance[1] discloses A method of fabricating an electromagnetic, EM, device (1000) according to Claim 1, the method comprising any one of the following processes: (1) additive manufacturing; (2) high-resolution 3D printing; (3) ultrahigh-resolution 3D printing; (4) femtosecond laser-induced 3D printing based on two-photon polymerization (TTP); (5) semiconductor device fabrication; (6) laser milling (para 0083)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pance[1] (US 2021/0013613 published Jan. 14, 2021) as applied to claim 1 above, and further in view of Pance[2] (US 2022/0271440 published Aug 25, 2022).
Claim 4: Pance[1] does not specifically disclose each DRA of the plurality of DRAs is a solid, non-hollow, construct.
Pance[2] discloses a DRA array wherein each DRA of the plurality of DRAs is a solid, non-hollow, construct (para 0042, 0061, 0062)
It would have been obvious to modify the invention such that it comprised the above limtations, as taught by Pance[2] in order to ease manufacturing challenges (Pance[2] para 0002, 0003, 0164)
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pance[1] (US 2021/0013613 published Jan. 14, 2021)
Claim 14: Pance[1] does not specifically disclose the inwardly tapered 3D shape (3150) has a taper angle α of equal to or greater than 20-degrees and equal to or less than 35-degrees; alternatively, equal to or greater than 25-degrees and equal to or less than 30-degrees. However, the taper angle is a design choice based on expected outcomes from a limited selection of possible taper angles. As such, it would have been obvious to modify the invention such that it comprised the above taper angles as it would yield predictable results which one of ordinary skill in the art would select based on a desired result.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pance[1] (US 2021/0013613 published Jan. 14, 2021) as applied to claim 1 above, and further in view of Plettemeier (US 2013/0009848)
Claim 23: Pance[1] does not specifically disclose the IC chip is capable of being configured to activate or deactivate certain ones of the plurality of DRAs in the DRA subarray so as to effect beam shaping or beam steering within the EM device
Plettemeir discloses an antenna array comprising dielectric resonator antennas (fig 1, para 0076) wherein the IC chip is capable of being configured to activate or deactivate certain ones of the plurality of DRAs in the DRA subarray so as to effect beam shaping or beam steering within the EM device (para 0053, 0070)
It would have been obvious to modify the invention such that it comprised the above limitations, in order to utilize a known beam shaping method which is easily implemented.
Claim(s) 25-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pance[1] (US 2021/0013613 published Jan. 14, 2021) as applied to claim 1 above, and further in view of Pance[3] (US 2018/0241129)
Claim 25: Pance[1] does not specifically disclose an encapsulant disposed encapsulating the IC chip, the waveguide, and DRA subarray
Pance[3] discloses a DRA array (fig 1a, 1b) comprising an IC chip (para 0103) and waveguide (para 0039, 0060) further comprising an encapsulant disposed encapsulating the IC chip, the waveguide, and DRA subarray (para 0033-0037, 0040)
It would have been obvious to modify the invention such that it comprised the above limitations, as taught by Pance[3] in order to protect the antenna array from environmental factors.
Claim 26: Pance[3] discloses the encapsulant comprises a dielectric material (para 0033-0037, 0040, 0062)
Claim 27: Pance[3] discloses the dielectric material of the encapsulant has a Dk value greater than 1 and equal to or less than 5, alternatively equal to or greater than 2 and equal to or less than 4 (para 0033-0037, 0040, 0062)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M BYTHROW whose telephone number is (571)270-1468. The examiner can normally be reached on Monday-Friday 830am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Resha Desai can be reached at (571) 270-7792. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M BYTHROW/Primary Examiner, Art Unit 3648
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