DETAILED ACTION
This office action is in response to the application filed on 12/13/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/01/2026 has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in claims 8, 10, 12, 19 and 21-22. Therefore, the “a bias circuit configured to receive the first ramp signal”, “slope compensation circuit configure to generate the ramp signal in response… the clock signal”, “the first terminal of t4he compensation capacitor is coupled to the PWM Filter circuit to receive the first ramp signal” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 9 and 20 are objected to because of the following informalities: Claim 9 and 20 recite “second capacitor is coupled to the first terminal of the first capacitor” this should be “second capacitor is coupled to a first terminal of a first capacitor”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8, 13-16 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fan US 2018/0248479.
Regarding Claim 1, Fan teaches (Figures 1-10) a control circuit (controller at 200) for a switching converter, wherein the switching converter (buck converter) having at least one power switch (at 270) is configured to covert an input voltage (Vin) into an output voltage (Vout) in response to a pulse-width modulation (PWM) control signal (PWM), and the control circuit comprises: a compensation circuit (at 214-216) configured to generate a compensation signal (Vctrl) in response to the output voltage and a reference signal (at 216); a ramp generation circuit (710 and 720) configured to generate a ramp signal (vramp) in response to the PWM control signal (Pwm int); a comparison circuit (220) configured to provide a comparison signal (from 220) in response to the compensation signal and the ramp signal (vramp and Vctrl); and a logic circuit (240) configured to provide the PWM control signal in response to the comparison signal and a clock signal (from 250). (For Example: Par. 34-51)
Regarding Claims 2 and 15, Fan teaches (Figures 1-10) wherein a DC bias of the ramp signal (Vramp) is proportional to the input voltage (Vin, par. 87-88).
Regarding Claims 3-4, Fan teaches (Figures 1-10) wherein the PWM control signal (PWM) is at a first voltage level when a voltage value of the ramp signal reaches a voltage value of the compensation signal (with 1002, loop comparator R input and the Q output); wherein the PWM control signal (PWM) is at a second voltage level in response to the clock signal (1002 with the set input). (For Example: Par. 109-113)
Regarding Claims 5 and 16, Fan teaches (Figures 1-10) wherein the ramp generation circuit (710 and 720) comprises: a PWM filter circuit (712-714, Rramp and Cramp) configured to filter the PWM control signal (PWM) and generate a first ramp signal (Vramp, see fig. 7). (For Example: Par. 87-99)
Regarding Claims 8 and 19, Fan teaches (Figures 1-10) wherein the ramp generation circuit (712-714, Rramp and Cramp) further comprises: a bias circuit (714) configured to receive the first ramp signal and adjust a DC bias of the first ramp signal to provide the ramp signal (par. 87-88 ). (For Example: Par. 87-99)
Regarding Claims 13-14, Fan teaches (Figures 1-10) a control circuit (controller at 200) for a switching converter, wherein the switching converter (buck converter) having at least one power switch (at 270) is configured to covert an input voltage (Vin) into an output voltage (Vout) in response to a pulse-width modulation (PWM) control signal (PWM), and the control circuit comprises: a compensation circuit (at 214-216) configured to generate a compensation signal (Vctrl) in response to the output voltage and a reference signal (at 216); a ramp generation circuit (710 and 720) configured to generate a ramp signal (vramp) in response to the PWM control signal (Pwm int); a comparison circuit (220) configured to provide a comparison signal (from 220) in response to the compensation signal and the ramp signal (vramp and Vctrl); and a logic circuit (240) configured to provide the PWM control signal in response to the comparison signal and a clock signal (from 250); wherein the PWM control signal (PWM) is at a first voltage level when a voltage value of the ramp signal reaches a voltage value of the compensation signal (with 1002, loop comparator R input and the Q output); wherein the PWM control signal (PWM) is at a second voltage level in response to the clock signal (1002 with the set input). (For Example: Par. 109-113)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-7 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fan in view of Huang US 9755519.
Regarding Claims 6 and 17, Fan teaches (Figures 1-10) wherein the ramp generation circuit (710-720) further comprises: a filter circuit (722) configured to filter the first ramp signal and generate a second ramp signal (output of 722). (For Example: Par. 86-99)
Fan does not teach a high-pass filter circuit.
Huang teaches (Figure 3 and 16) a high-pass filter circuit (208 or 212).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Fan to include a high-pass filter circuit as taught by Huang to have good stability and transient response.
Regarding Claims 7 and 18, Fan teaches (Figures 1-10) wherein the PWM filter circuit (712-714, Rramp and Cramp) comprises a first resistor and a first capacitor (Rramp and Cramp); wherein a first terminal of the first resistor (Rramp) is configured to receive the PWM control signal (PWM), and a second terminal of the first resistor is coupled to a first terminal of the first capacitor (Cramp) to provide the first ramp signal (Vramp). (For Example: Par. 86-99)
Fan does not teach the high-pass filter circuit comprises a second capacitor and a second resistor; and wherein a first terminal of the second capacitor is coupled to the first terminal of the first capacitor to receive the first ramp signal, and a second terminal of the second capacitor is coupled to a first terminal of the second resistor to provide the second ramp signal.
Huang teaches (Figure 3 and 16) the high-pass filter circuit (212) comprises a second capacitor and a second resistor (see fig. 16); and wherein a first terminal of the second capacitor is coupled to the first terminal of the first capacitor to receive the first ramp signal (vhf1; see fig. 3, from 210 to 212), and a second terminal of the second capacitor (see fig. 16) is coupled to a first terminal of the second resistor to provide the second ramp signal (Vhf2). (For Example: Col. 6 and Col. 11)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Fan to include the high-pass filter circuit comprises a second capacitor and a second resistor; and wherein a first terminal of the second capacitor is coupled to the first terminal of the first capacitor to receive the first ramp signal, and a second terminal of the second capacitor is coupled to a first terminal of the second resistor to provide the second ramp signal as taught by Huang to have good stability and transient response.
Claim(s) 10-11 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fan in view of Hawkes US 2011/0062932.
Regarding Claim 21, Fan teaches (Figures 1-10) wherein the ramp generation circuit. (For Example: Par. 86-99)
Fan does not teach wherein the ramp generation circuit further comprises: a slope compensation circuit configured to generate the ramp signal in response to the first ramp signal, the clock signal and the PWM control signal, wherein the ramp signal is a periodic signal having a constant frequency set by the clock signal.
Hawkes teaches (Figures 7-8) a slope compensation circuit (adder and 1-shot and c3) configured to generate the ramp signal (Vr2) in response to the first ramp signal (ramp), the clock signal (clk) and the PWM control signal (pwm), wherein the ramp signal is a periodic signal having a constant frequency set by the clock signal (see fig. 7-8). (For Example: Par. 85-93)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Fan to include wherein the ramp generation circuit further comprises: a slope compensation circuit configured to generate the ramp signal in response to the first ramp signal, the clock signal and the PWM control signal, wherein the ramp signal is a periodic signal having a constant frequency set by the clock signal, as taught by Hawkes to generate a constant average output.
Allowable Subject Matter
Claim 9, 12, 20 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claims 9 and 20; prior art of record fails to disclose either by itself or in combination: “…a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the first terminal of the first capacitor to receive the first ramp signal; a second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the second terminal of the second capacitor to provide the second ramp signal; wherein the bias circuit comprises: an operational amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the operational amplifier is configured to receive a bias voltage, and the output terminal of the operational amplifier is coupled to the second terminal of the second resistor; a first transistor having a first terminal, a second terminal and a control terminal, wherein the control terminal of the first transistor is coupled to the output terminal of the operational amplifier, and the second terminal of the first transistor is coupled to the second input terminal of the operational amplifier; and a second transistor having a first terminal, a second terminal and a control terminal, wherein the control terminal of the second transistor is coupled to the first terminal of the second resistor, and the second terminal of the second transistor is configured to provide a third ramp signal.”
Claims 12 and 22; prior art of record fails to disclose either by itself or in combination: “… wherein the slope compensation circuit comprises: a current source configured to provide a charging current; a compensation capacitor coupled in series with the current source, wherein the compensation capacitor has a first terminal and a second terminal, the first terminal of the compensation capacitor is coupled to the PWM filter circuit to receive the first ramp signal, and the second terminal of the compensation capacitor is configured to provide the ramp signal; and a control switch coupled in parallel with the compensation capacitor, wherein the control switch is controlled in response to the clock signal and the PWM control signal.”
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Conclusion
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/GUSTAVO A ROSARIO-BENITEZ/ Primary Examiner, Art Unit 2838
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