Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant application having Application No. 18/981,221 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The specification should be amended to reflect the status of all related applications, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
INFORMATION CONCERNING DRAWINGS
The applicant’s drawings submitted are acceptable for examination purposes.
STATUS OF CLAIM FOR PRIORITY IN THE APPLICATION
The instant application no. 18981221 filed 12/13/2024 is a Continuation of 18340756, filed 06/23/2023, now U.S. Patent # 12169453. Application 18340756 is a Continuation of 17308558, filed 05/05/2021, now U.S. Patent # 11687446. Application 17308558 is a Continuation of 16236897, filed 12/31/2018, now U.S. Patent # 11003576. Application 16236897 is a Continuation of 15814634, filed 11/16/2017, now U.S. Patent # 10223254.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statement(s) dated 12/18/2024, 12/18/2024 is/are acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy/ /(copies) of the PTOL-1449(s) initialed and dated by the examiner is/are attached to the instant office action.
REJECTIONS BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Note that (MPEP 804.0 (I.B.1)) states: A complete response to a nonstatutory double patenting (NDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional.
As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Therefore, an application must not be allowed unless the required compliant terminal disclaimer(s) is/are filed and/or the withdrawal of the nonstatutory double patenting rejection(s) is made of record by the examiner. See MPEP § 804.02, subsection VI, for filing terminal disclaimers required to overcome nonstatutory double patenting rejections in applications filed on or after June 8, 1995.
Claims 1-2, 4-6, 11-12, 15-16 and 19-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1, 2-3, 6-8, 15 and 18 of US 10223254 (Corresponding to Application No. 15/814634). Although the conflicting claims are not identical, they are not patentably distinct from each other because the claims in the parent disclose/obviate the subject matter of the claims in the instant application.
Claims of the instant application are compared to claims of the patent in the following table:
Instant Application
US 10223254 (Corresponding to Application No. 15/814634)
1. A device, comprising: memory; and a controller coupled to the memory and configured to: identify a first logical address map of a plurality of logical address maps as active, wherein while the first logical address map is active the first logical address map is used by the controller to access data stored in the memory; and
identify a second logical address map of the plurality of logical address maps as inactive.
2. The device of claim 1, wherein the controller is further configured to generate, in the memory, the first logical address map and the second logical address map of the plurality of logical address maps, wherein the second logical address map is identical to the first logical address map at a time of generation of the second logical address map.
4. The device of claim 1, wherein the second logical address map is inactive while the first logical address map is active.
5. The device of claim 1, wherein the controller is further configured to change the second logical address map while the first logical address map is identified as active.
6. The device of claim 5, wherein the controller is further configured to identify the second logical address map as active after the second logical address map is changed.
11. The device of claim 1, wherein the controller comprises a plurality of processors, each having a cache.
12. The device of claim 1, wherein the memory comprises non-volatile storage media; and the first logical address map is configured to map logical addresses defined in one or more namespaces to logical addresses defined in a capacity of the non-volatile storage media.
15. A method, comprising: identifying, by a controller of a device having a memory, a first logical address map of a plurality of logical address maps as active, wherein while the first logical address map is active the first logical address map is used by the controller to access data stored in the memory; and identifying, by the controller a second logical address map of the plurality of logical address maps as inactive.
16. The method of claim 15, further comprising identifying, after the second logical address map is changed, the second logical address map as active.
19. A non-transitory computer storage medium storing instructions which, when executed by a device, cause the device to perform a method, the method comprising: identifying, by a controller of a device having a memory, a first logical address map of a plurality of logical address maps as active, wherein while the first logical address map is active the first logical address map is used by the controller to access data stored in the memory; and identifying, by the controller a second logical address map of the plurality of logical address maps as inactive.
20. The non-transitory computer storage medium of claim 19, wherein the instructions are configured as a first component and a second component; wherein only one instance of the first component is allowed to run in the device at a time to modify a logical address map in the memory.
1. A computer storage device, comprising: a controller; non-volatile storage media; and firmware containing instructions which, when executed by the controller, instruct the controller to at least: identify a first copy of mapping data as active, the mapping data defining mapping, from logical block addresses in one or more namespaces configured on the non-volatile storage media, to logical block addresses in a capacity of the non-volatile storage media; cache the first copy in one or more memory areas in the computer storage device as one or more second copies of the mapping data in one or more running instances of a first component of the firmware;
replicate the first copy to create a third copy; implement changes in the third copy while the first copy is being identified as active; after the changes are made in the third copy, identify the third copy as active and simultaneously make the first copy inactive; and update the one or more second copies according to the third copy in response to making the third copy active and the first copy inactive.
Note the third copy is deemed inactive before it is made active
See claim 1 where the third copy is a copy or identical to the first copy
See claim 8
See claim 1
2. The computer storage device of claim 1, wherein the controller includes a plurality of processors that execute the one or more running instances of the first component of the firmware in parallel.
6. The computer storage device of claim 2, wherein the first component of the firmware is not allowed to change mapping, from logical block addresses in one or more namespaces configured on the non-volatile storage media, to logical block addresses in the capacity of the non-volatile storage media.
7. The computer storage device of claim 6, wherein the computer storage device contains no more than a single running instance of a second component of the firmware that is allowed to change mapping, from logical block addresses in one or more namespaces configured on the non-volatile storage media, to logical block addresses in the capacity of the non-volatile storage media.
8. The computer storage device of claim 7, further comprising: an active indicator, wherein the firmware causes the active indicator to identify the first copy as being active before the changes are implemented in the third copy and the third copy as being active after the changes are implemented in the third copy.
3. The computer storage device of claim 2, wherein the one or more memory areas are in cache memory of the plurality of processors.
See claims 6 and 7 above
15. A method implemented in a computer storage device, the method comprising: storing a first copy of mapping data, the mapping data defining mapping, from logical block addresses in one or more namespaces configured on a non-volatile storage media of the computer storage device, to logical block addresses in a capacity of the non-volatile storage media; configuring an active indicator to identify the first copy as active; caching the first copy in one or more memory areas in the computer storage device as one or more second copies of the mapping data in one or more running instances of a first firmware component being executed by a controller of the computer storage device; replicating the first copy to create a third copy; changing the third copy while the first copy is being identified as active; after changing the third copy, changing the active indicator to identify the third copy as active and thus simultaneously render the first copy inactive; and in response to the changing of the active indicator, updating the second copies according to the third copy.
Note the third copy is deemed inactive before it is made active
See claim 15 where the third copy is a copy or identical to the first copy
18. A non-transitory computer storage medium storing instructions which, when executed by a controller of a computer storage device, cause the controller to perform a method, the method comprising: storing a first copy of mapping data, the mapping data defining mapping, from logical block addresses in one or more namespaces configured on a non-volatile storage media of the computer storage device, to logical block addresses in a capacity of the non-volatile storage media; configuring an active indicator to identify the first copy as active; caching the first copy in one or more memory areas in the computer storage device as one or more second copies of the mapping data in one or more running instances of a first instruction component being executed by a controller of the computer storage device; replicating the first copy to create a third copy; changing the third copy while the first copy is being identified as active; after changing the third copy, changing the active indicator to identify the third copy as active and thus simultaneously rendering the first copy inactive; and in response to the changing of the active indicator, updating the second copies according to the third copy.
Note the third copy is deemed inactive before it is made active
See claim 7
Claims 1-2, 4-6, 11-13, 15-17 and 19-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-9 and 15-19 of US 11003576 (Corresponding to Application No. 16/236897). Although the conflicting claims are not identical, they are not patentably distinct from each other because the claims in the parent disclose/obviate the subject matter of the claims in the instant application.
Claims of the instant application are compared to claims of the patent in the following table:
Instant Application
US 11003576 (Corresponding to Application No. 16/236897)
1. A device, comprising: memory; and a controller coupled to the memory and configured to: identify a first logical address map of a plurality of logical address maps as active, wherein while the first logical address map is active the first logical address map is used by the controller to access data stored in the memory; and identify a second logical address map of the plurality of logical address maps as inactive.
2. The device of claim 1, wherein the controller is further configured to generate, in the memory, the first logical address map and the second logical address map of the plurality of logical address maps, wherein the second logical address map is identical to the first logical address map at a time of generation of the second logical address map.
4. The device of claim 1, wherein the second logical address map is inactive while the first logical address map is active.
5. The device of claim 1, wherein the controller is further configured to change the second logical address map while the first logical address map is identified as active.
6. The device of claim 5, wherein the controller is further configured to identify the second logical address map as active after the second logical address map is changed.
11. The device of claim 1, wherein the controller comprises a plurality of processors, each having a cache.
12. The device of claim 1, wherein the memory comprises non-volatile storage media; and the first logical address map is configured to map logical addresses defined in one or more namespaces to logical addresses defined in a capacity of the non-volatile storage media.
13. The device of claim 1, wherein the memory further includes a volatile random access memory; and the first logical address map and the second logical address are stored in the volatile random access memory.
15. A method, comprising: identifying, by a controller of a device having a memory, a first logical address map of a plurality of logical address maps as active, wherein while the first logical address map is active the first logical address map is used by the controller to access data stored in the memory; and identifying, by the controller a second logical address map of the plurality of logical address maps as inactive.
16. The method of claim 15, further comprising identifying, after the second logical address map is changed, the second logical address map as active.
17. The method of claim 16, further comprising communicating, in response to the second logical address map being identified as active, with a cache of the device to synchronize the first logical address map loaded in the cache with the second logical address map.
19. A non-transitory computer storage medium storing instructions which, when executed by a device, cause the device to perform a method, the method comprising: identifying, by a controller of a device having a memory, a first logical address map of a plurality of logical address maps as active, wherein while the first logical address map is active the first logical address map is used by the controller to access data stored in the memory; and identifying, by the controller a second logical address map of the plurality of logical address maps as inactive.
20. The non-transitory computer storage medium of claim 19, wherein the instructions are configured as a first component and a second component; wherein only one instance of the first component is allowed to run in the device at a time to modify a logical address map in the memory.
1. A solid state drive, comprising: random access memory; non-volatile storage media; and a controller having a plurality of processors, the controller configured to at least: store a first copy of a namespace map in the random access memory; configure the first copy of the namespace map as active; cache the first copy as one or more second copies in one or more processors in the plurality of processors; replicate, in the random access memory, the first copy as a third copy; change the third copy in the random access memory while the first copy is configured as active; configure the third copy as active and the first copy as inactive after the changing of the third copy in the random access memory; and update the one or more second copies in the one or more processors according to the third copy that is configured as active.
Note the third copy is deemed inactive before it is made active
See claims 1 and 9 where the third copy is a copy or identical to the first copy.
See claim 9
See claim 1
See claim 1
2. The solid state drive of claim 1, wherein the one or more processors are configured to map, using the one or more second copies, between: logical block addresses in one or more namespaces configured on the non-volatile storage media; and logical block addresses in a capacity of the non-volatile storage media.
3. The solid state drive of claim 2, wherein the one or more processors are configured to cache the one or more second copies in cache memory of the one or more processors.
4. The solid state drive of claim 3, wherein the controller is configured to update the one or more second copies cached in the one or more processors in accordance with a cache coherence protocol.
See claim 2
5. The solid state drive of claim 2, wherein the random access memory includes volatile dynamic random access memory.
6. The solid state drive of claim 2, wherein the one or more processors are not permitted to modify the one or more second copies other than updating according to a copy of the namespace map that is configured as active in the random access memory.
7. The solid state drive of claim 6, wherein no more than a single running instance of a component of firmware of the solid state drive is permitted to change a copy of the namespace map that is configured as inactive in the random access memory.
8. The solid state drive of claim 7, further comprising: an active indicator, wherein a copy of the namespace map in the random access memory identified by the active indicator is configured to be active.
9. The solid state drive of claim 8, wherein any copy in the random access memory that is not being identified by the active indicator is configured as inactive.
15. A method implemented in a solid state drive, the method comprising: storing a first copy of a namespace map in random access memory of the solid state drive; configuring the first copy as active; caching the first copy as one or more second copies in one or more processors of the solid state drive; replicating the first copy in the random access memory as a third copy; changing the third copy while the first copy is configured as active; configuring the third copy as active and the first copy as inactive after the changing of the third copy; and updating the one or more second copies in the one or more processors according to the third copy that is configured as active.
See claims 1 and 9 where the third copy is a copy or identical to the first copy. See claim 9 as well
See claim 15
16. The method of claim 15, further comprising: mapping, using the one or more second copies of the namespace map, between: logical block addresses in one or more namespaces configured on non-volatile storage media of the solid state drive; and logical block addresses in a storage capacity of the solid state drive.
17. The method of claim 16, wherein the update of the one or more second copies cached in the one or more processors is in accordance with a cache coherence protocol; and the configuring the third copy as active and the first copy as inactive is performed by replacing, in an active indicator of the solid state drive, an identifier of the first copy with an identifier of the second copy.
18. A non-transitory computer storage medium storing instructions which, when executed in a solid state drive, cause the solid state drive to perform a method, the method comprising: storing a first copy of a namespace map in random access memory of the solid state drive; configuring the first copy as active; caching the first copy as one or more second copies in one or more processors of the solid state drive; replicating the first copy in the random access memory as a third copy; changing the third copy while the first copy is configured as active; configuring the third copy as active and the first copy as inactive after the changing of the third copy; and updating the one or more second copies in the one or more processors according to the third copy that is configured as active.
See claims 1 and 9 where the third copy is a copy or identical to the first copy. See claim 9 as well
See claim 7
Claims 1-5, 11-13, 15-17 and 19-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-9, 15-16 and 18-19 of US 11687446 (Corresponding to Application No. 17/308558). Although the conflicting claims are not identical, they are not patentably distinct from each other because the claims in the parent disclose/obviate the subject matter of the claims in the instant application.
Claims of the instant application are compared to claims of the patent in the following table:
Instant Application
US 11687446 (Corresponding to Application No. 17/308558)
1. A device, comprising: memory; and a controller coupled to the memory and configured to: identify a first logical address map of a plurality of logical address maps as active, wherein while the first logical address map is active the first logical address map is used by the controller to access data stored in the memory; and identify a second logical address map of the plurality of logical address maps as inactive.
2. The device of claim 1, wherein the controller is further configured to generate, in the memory, the first logical address map and the second logical address map of the plurality of logical address maps, wherein the second logical address map is identical to the first logical address map at a time of generation of the second logical address map.
3. The device of claim 1, wherein the controller is further configured to cause the first logical address map to be loaded in response to a request to load from the memory a map for logical addresses.
4. The device of claim 1, wherein the second logical address map is inactive while the first logical address map is active.
5. The device of claim 1, wherein the controller is further configured to change the second logical address map while the first logical address map is identified as active.
11. The device of claim 1, wherein the controller comprises a plurality of processors, each having a cache.
12. The device of claim 1, wherein the memory comprises non-volatile storage media; and the first logical address map is configured to map logical addresses defined in one or more namespaces to logical addresses defined in a capacity of the non-volatile storage media.
13. The device of claim 1, wherein the memory further includes a volatile random access memory; and the first logical address map and the second logical address are stored in the volatile random access memory.
15. A method, comprising: identifying, by a controller of a device having a memory, a first logical address map of a plurality of logical address maps as active, wherein while the first logical address map is active the first logical address map is used by the controller to access data stored in the memory; and identifying, by the controller a second logical address map of the plurality of logical address maps as inactive.
16. The method of claim 15, further comprising identifying, after the second logical address map is changed, the second logical address map as active.
17. The method of claim 16, further comprising communicating, in response to the second logical address map being identified as active, with a cache of the device to synchronize the first logical address map loaded in the cache with the second logical address map.
19. A non-transitory computer storage medium storing instructions which, when executed by a device, cause the device to perform a method, the method comprising: identifying, by a controller of a device having a memory, a first logical address map of a plurality of logical address maps as active, wherein while the first logical address map is active the first logical address map is used by the controller to access data stored in the memory; and identifying, by the controller a second logical address map of the plurality of logical address maps as inactive.
20. The non-transitory computer storage medium of claim 19, wherein the instructions are configured as a first component and a second component; wherein only one instance of the first component is allowed to run in the device at a time to modify a logical address map in the memory.
1. A device comprising: random access memory; non-volatile storage media; and a plurality of processors, configured to at least: identify a first copy of a namespace map in the random access memory as active; load, by a processor in the plurality of processors, the first copy from the random access memory as a second copy of the namespace map; generate, in the random access memory, a third copy of the namespace map from the first copy while the first copy is identified as active; identify the third copy as active and the first copy as inactive; and update the second copy in the processor according to the third copy identified as active.
See claims 1 and 9 where the third copy is a copy or identical to the first copy.
See claim 1
See claims 1 and 9
2. The device of claim 1, wherein the plurality of processors are configured to map, using the one or more second copies, between: logical block addresses in one or more namespaces configured on the non-volatile storage media; and logical block addresses in a capacity of the non-volatile storage media.
3. The device of claim 2, wherein the plurality of processors are configured to cache the one or more second copies in cache memory of the one or more processors.
4. The device of claim 3, wherein the controller is configured to update the one or more second copies cached in the plurality of processors in accordance with a cache coherence protocol.
5. The device of claim 2, wherein the random access memory includes volatile dynamic random access memory.
6. The device of claim 2, wherein the plurality of processors are not permitted to modify the one or more second copies other than updating according to a copy of the namespace map that is configured as active in the random access memory.
See claims 3-4
See claim 2
See claims 5 and 2
7. The device of claim 6, wherein no more than a single running instance of a component of firmware of a solid state drive is permitted to change a copy of the namespace map that is configured as inactive in the random access memory.
8. The device of claim 7, further comprising: an active indicator, wherein a copy of the namespace map in the random access memory identified by the active indicator is configured to be active.
9. The device of claim 8, wherein any copy in the random access memory that is not being identified by the active indicator is configured as inactive.
15. A method implemented in a device, the method comprising: storing a first copy of a namespace map in random access memory of a solid state drive; configuring the first copy as active; caching the first copy as one or more second copies in one or more processors of the solid state drive; replicating the first copy in the random access memory as a third copy; changing the third copy while the first copy is configured as active; configuring the third copy as active and the first copy as inactive after the changing of the third copy; and updating the one or more second copies in the one or more processors according to the third copy that is configured as active.
16. A method comprising: storing, as active, a first copy of a namespace map in random access memory of a device; caching the first copy as second copies in a plurality of processors of the device; generating a third copy from the first copy in the random access memory while the first copy is configured as active; changing the third copy as active and the first copy as inactive; and updating the second copies in the processors according to the third copy that is active.
18. The method of claim 16, wherein the update of the one or more second copies cached in the plurality of processors is in accordance with a cache coherence protocol; and configuring the third copy as active and the first copy as inactive is performed by replacing, in an active indicator of the solid state drive, an identifier of the first copy with an identifier of the second copy.
19. A non-transitory computer storage medium storing instructions which, when executed in a device, cause the device to perform a method, the method comprising: storing, as active, a first copy of a namespace map in random access memory of a device; caching the first copy as second copies in a plurality of processors of the device; generating a third copy from the first copy in the random access memory while the first copy is configured as active; changing the third copy as active and the first copy as inactive; and updating the second copies in the processors according to the third copy that is active.
See claim 7
Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-11, 18 and 20 of US 12169453 (Corresponding to Application No. 18/340756). Although the conflicting claims are not identical, they are not patentably distinct from each other because the claims in the parent disclose/obviate the subject matter of the claims in the instant application.
Claims of the instant application are compared to claims of the patent in the following table:
Instant Application
US 12169453 (Corresponding to Application No. 18/340756)
1. A device, comprising: memory; and a controller coupled to the memory and configured to: identify a first logical address map of a plurality of logical address maps as active, wherein while the first logical address map is active the first logical address map is used by the controller to access data stored in the memory; and identify a second logical address map of the plurality of logical address maps as inactive.
2. The device of claim 1, wherein the controller is further configured to generate, in the memory, the first logical address map and the second logical address map of the plurality of logical address maps, wherein the second logical address map is identical to the first logical address map at a time of generation of the second logical address map.
3. The device of claim 1, wherein the controller is further configured to cause the first logical address map to be loaded in response to a request to load from the memory a map for logical addresses.
4. The device of claim 1, wherein the second logical address map is inactive while the first logical address map is active.
5. The device of claim 1, wherein the controller is further configured to change the second logical address map while the first logical address map is identified as active.
6. The device of claim 5, wherein the controller is further configured to identify the second logical address map as active after the second logical address map is changed.
7. The device of claim 6, wherein the controller is further configured to, after the second logical address map is identified as active, cause the second logical address map to be loaded in response to a request to load from the memory a map for logical addresses.
8. The device of claim 1, wherein the controller is further configured to: receive, during a time period in which the first logical address map is identified as active, a first request to load from the memory a map for logical addresses; and provide, in response to the first request, the first logical address map to a cache.
9. The device of claim 8, wherein the controller is further configured to: communicate, in response to the second logical address map being identified as active, with the cache to synchronize the first logical address map loaded in the cache with the second logical address map.
10. The device of claim 9, wherein the cache is configured in a core of a processor of the controller.
11. The device of claim 1, wherein the controller comprises a plurality of processors, each having a cache.
12. The device of claim 1, wherein the memory comprises non-volatile storage media; and the first logical address map is configured to map logical addresses defined in one or more namespaces to logical addresses defined in a capacity of the non-volatile storage media.
13. The device of claim 1, wherein the memory further includes a volatile random access memory; and the first logical address map and the second logical address are stored in the volatile random access memory.
14. The device of claim 13, wherein the controller is configured with firmware having a first component and a second component; wherein only one instance of the first component is allowed to run in the device at a time to modify a logical address map in the volatile random access memory that is not identified as active; and wherein multiple instances of the second components are allowed to run concurrently in the device but not allowed to modify a logical address map in the volatile random access memory.
15. A method, comprising: identifying, by a controller of a device having a memory, a first logical address map of a plurality of logical address maps as active, wherein while the first logical address map is active the first logical address map is used by the controller to access data stored in the memory; and identifying, by the controller a second logical address map of the plurality of logical address maps as inactive.
16. The method of claim 15, further comprising identifying, after the second logical address map is changed, the second logical address map as active.
17. The method of claim 16, further comprising communicating, in response to the second logical address map being identified as active, with a cache of the device to synchronize the first logical address map loaded in the cache with the second logical address map.
18. The method of claim 15, further comprising: receiving, during a time period in which the first logical address map is identified as active, a first request to load from the memory a map for logical addresses; and providing, in response to the first request, the first logical address map to a cache in the device.
19. A non-transitory computer storage medium storing instructions which, when executed by a device, cause the device to perform a method, the method comprising: identifying, by a controller of a device having a memory, a first logical address map of a plurality of logical address maps as active, wherein while the first logical address map is active the first logical address map is used by the controller to access data stored in the memory; and identifying, by the controller a second logical address map of the plurality of logical address maps as inactive.
20. The non-transitory computer storage medium of claim 19, wherein the instructions are configured as a first component and a second component; wherein only one instance of the first component is allowed to run in the device at a time to modify a logical address map in the memory.
1. A device, comprising: memory; and a controller coupled to the memory and configured to: generate, in the memory, a first logical address map and a second logical address map that is identical to the first logical address map; identify the first logical address map as active to cause the first logical address map to be loaded in response to a request to load from the memory a map for logical addresses; implement one or more changes in the second logical address map while the first logical address map is identified as active; and identify, after the one or more changes, the second logical address map as active to cause the second logical address map to be loaded in response to a request to load from the memory a map for logical addresses.
Note the second logical address map is deemed inactive before it is made active
See claim 1 above
2. The device of claim 1, wherein the controller is further configured to: receive, during a time period in which the first logical address map is identified as active, a first request to load from the memory a map for logical addresses; and provide, in response to the first request, the first logical address map to a cache.
See claim 1
See claim 1
See claim 1
See claim 1
See claim 2
3. The device of claim 2, wherein the controller is further configured to: communicate, in response to the second logical address map being identified as active, with the cache to synchronize the first logical address map loaded in the cache with the second logical address map.
4. The device of claim 3, wherein the cache is configured in a core of a processor of the controller.
5. The device of claim 4, wherein the first logical address map and the second logical address are generated and stored in the memory separate from the controller.
6. The device of claim 5, wherein the controller comprises a plurality of processors, each having a cache.
7. The device of claim 6, wherein the memory includes non-volatile storage media; and the first logical address map is configured to map logical addresses defined in one or more namespaces to logical addresses defined in a capacity of the non-volatile storage media.
8. The device of claim 7, wherein the memory further includes a volatile random access memory; and the first logical address map and the second logical address are generated and stored in the volatile random access memory.
9. The device of claim 8, wherein the controller is configured with firmware having a first component and a second component; wherein only one instance of the first component is allowed to run in the device at a time to modify a logical address map in the volatile random access memory that is not identified as active; and wherein multiple instances of the second components are allowed to run concurrently in the device but not allowed to modify a logical address map in the volatile random access memory.
10. A method, comprising: generating, by a controller of a device and in memory of the device, a first logical address map and a second logical address map that is identical to the first logical address map; identifying the first logical address map as active to cause the first logical address map to be loaded in response to a request to load a map for logical addresses; implementing one or more changes in the second logical address map while the first logical address map is identified as active; and identifying, after the one or more changes, the second logical address map as active to cause the second logical address map to be loaded in response to a request to load a map for logical addresses.
See claim 12
11. The method of claim 10, further comprising: receiving, during a time period in which the first logical address map is identified as active, a first request to load from the memory a map for logical addresses; and providing, in response to the first request, the first logical address map to a cache in the device.
18. A non-transitory computer storage medium storing instructions which, when executed by a device, cause the device to perform a method, the method comprising: generating, by a controller of the device and in memory of the device, a first logical address map and a second logical address map that is identical to the first logical address map; identifying the first logical address map as active to cause the first logical address map to be loaded in response to a request to load a map for logical addresses; implementing one or more changes in the second logical address map while the first logical address map is identified as active; and identifying, after the one or more changes, the second logical address map as active to cause the second logical address map to be loaded in response to a request to load a map for logical addresses.
20. The non-transitory computer storage medium of claim 18, wherein the instructions are configured as a first component and a second component; wherein only one instance of the first component is allowed to run in the device at a time to modify a logical address map in the memory.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, 15-16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Belevich et al. (US 2005/0223186) in view of Willman et al. (US 2003/0200402).
1. A device, comprising: memory; and a controller coupled to the memory and configured to: identify a first logical address map of a plurality of logical address maps as active, wherein while the first logical address map is active the first logical address map is used by the controller to access data stored in the memory; and [Belevich teaches translation maps A and B (fig. 11 and related text) where “[0043] Entire translation maps can be upgraded and then changed atomically using a similar approach. Referring to FIG. 10, a selection bit 168 of the block switching logic 142C determines whether translation map A or translation map B is applied to the external addresses. Updating a translation map can be achieved by identifying one of the translation maps (e.g., map A) as the active map and the other map (e.g., map B) as the inactive map” ] and where Belevich maps translate external or physical addresses to internal addresses (see par. 0037) but does not expressly refer to the maps as logical address maps
identify a second logical address map of the plurality of logical address maps as inactive [Belevich teaches “[0043] Entire translation maps can be upgraded and then changed atomically using a similar approach. Referring to FIG. 10, a selection bit 168 of the block switching logic 142C determines whether translation map A or translation map B is applied to the external addresses. Updating a translation map can be achieved by identifying one of the translation maps (e.g., map A) as the active map and the other map (e.g., map B) as the inactive map, the inactive map is then updated in the background while the active map is in use.”].
Regarding the maps as logical address maps, Willman teaches [“With virtual addressing, as is known in the art, a virtual address facility such as the computer's memory management unit (MMU) uses a set of translation maps to convert a virtual address into a physical address. When a system supports virtual addressing, any memory location can be made accessible by editing the address translation maps to assign a virtual address to the desired physical memory location.” (par. 0003) where “[0081] FIG. 4 shows an exemplary process for evaluating whether a new address translation map may be activated. The example of FIG. 4 assumes that a new address translation map is activated by writing a pointer to the map's base address into a defined storage location (e.g., storage location 201 shown in FIG. 2). However, it will be understood that the invention is not limited to the situation where address translation maps are activated in this manner, and that the process of FIG. 4 can be applied to any system that allows the currently-active address translation map to be replaced with another map.”].
Belevich and Willman are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Belevich to have the maps of Belevich as logical address maps such as the maps of Willman since doing so would facilitate management of the logical to physical address translation and Willman explains [“[0002] The present invention relates generally to the field of computer memory. More particularly, the invention provides a technique for achieving memory isolation by controlling changes to an address translation map that is used to convert virtual addresses to physical addresses.”].
Therefore, it would have been obvious to combine Belevich and Willman for the benefit of creating a storage system/method to obtain the invention as specified in claim 1.
3. The device of claim 1, wherein the controller is further configured to cause the first logical address map to be loaded in response to a request to load from the memory a map for logical addresses [Belevich teaches “[0043] Entire translation maps can be upgraded and then changed atomically using a similar approach. Referring to FIG. 10, a selection bit 168 of the block switching logic 142C determines whether translation map A or translation map B is applied to the external addresses. Updating a translation map can be achieved by identifying one of the translation maps (e.g., map A) as the active map and the other map (e.g., map B) as the inactive map, the inactive map is then updated in the background while the active map is in use.” Where applying a given translation map for a translation corresponds to loading the map. Willman additionally teaches “[0081] FIG. 4 shows an exemplary process for evaluating whether a new address translation map may be activated. The example of FIG. 4 assumes that a new address translation map is activated by writing a pointer to the map's base address into a defined storage location (e.g., storage location 201 shown in FIG. 2). However, it will be understood that the invention is not limited to the situation where address translation maps are activated in this manner, and that the process of FIG. 4 can be applied to any system that allows the currently-active address translation map to be replaced with another map.” Where the currently active map as indicated by storage location 201 is interpreted as loaded].
4. The device of claim 1, wherein the second logical address map is inactive while the first logical address map is active [Belevich teaches “[0043] Entire translation maps can be upgraded and then changed atomically using a similar approach. Referring to FIG. 10, a selection bit 168 of the block switching logic 142C determines whether translation map A or translation map B is applied to the external addresses. Updating a translation map can be achieved by identifying one of the translation maps (e.g., map A) as the active map and the other map (e.g., map B) as the inactive map, the inactive map is then updated in the background while the active map is in use. Willman teaches “[0081] FIG. 4 shows an exemplary process for evaluating whether a new address translation map may be activated. The example of FIG. 4 assumes that a new address translation map is activated by writing a pointer to the map's base address into a defined storage location (e.g., storage location 201 shown in FIG. 2). However, it will be understood that the invention is not limited to the situation where address translation maps are activated in this manner, and that the process of FIG. 4 can be applied to any system that allows the currently-active address translation map to be replaced with another map.”].
5. The device of claim 1, wherein the controller is further configured to change the second logical address map while the first logical address map is identified as active [Belevich teaches “[0043] Entire translation maps can be upgraded and then changed atomically using a similar approach. Referring to FIG. 10, a selection bit 168 of the block switching logic 142C determines whether translation map A or translation map B is applied to the external addresses. Updating a translation map can be achieved by identifying one of the translation maps (e.g., map A) as the active map and the other map (e.g., map B) as the inactive map, the inactive map is then updated in the background while the active map is in use...”].
6. The device of claim 5, wherein the controller is further configured to identify the second logical address map as active after the second logical address map is changed [Belevich teaches “Updating a translation map can be achieved by identifying one of the translation maps (e.g., map A) as the active map and the other map (e.g., map B) as the inactive map, the inactive map is then updated in the background while the active map is in use. After the active translation map is updated, the selection bit can be switched to make translation map B the active translation map and translation map A the inactive map. The atomic switch between translation maps prevents a partially upgraded translation map from being used to identify an internal address” (par. 0043)].
7. The device of claim 6, wherein the controller is further configured to, after the second logical address map is identified as active, cause the second logical address map to be loaded in response to a request to load from the memory a map for logical addresses [Belevich teaches [0043] Entire translation maps can be upgraded and then changed atomically using a similar approach. Referring to FIG. 10, a selection bit 168 of the block switching logic 142C determines whether translation map A or translation map B is applied to the external addresses. Updating a translation map can be achieved by identifying one of the translation maps (e.g., map A) as the active map and the other map (e.g., map B) as the inactive map, the inactive map is then updated in the background while the active map is in use. After the active translation map is updated, the selection bit can be switched to make translation map B the active translation map and translation map A the inactive map. The atomic switch between translation maps prevents a partially upgraded translation map from being used to identify an internal address.” where identifying the second map as active and applying a given translation map identified as active for a translation corresponds to loading the map. Willman additionally teaches “[0081] FIG. 4 shows an exemplary process for evaluating whether a new address translation map may be activated. The example of FIG. 4 assumes that a new address translation map is activated by writing a pointer to the map's base address into a defined storage location (e.g., storage location 201 shown in FIG. 2). However, it will be understood that the invention is not limited to the situation where address translation maps are activated in this manner, and that the process of FIG. 4 can be applied to any system that allows the currently-active address translation map to be replaced with another map.” Where the currently active map as indicated by storage location 201 is interpreted as loaded].
15. A method, comprising: identifying, by a controller of a device having a memory, a first logical address map of a plurality of logical address maps as active, wherein while the first logical address map is active the first logical address map is used by the controller to access data stored in the memory; and identifying, by the controller a second logical address map of the plurality of logical address maps as inactive [The rationale in the rejection of claim 1 is herein incorporated].
16. The method of claim 15, further comprising identifying, after the second logical address map is changed, the second logical address map as active [The rationale in the rejection of claim 6 is herein incorporated].
19. A non-transitory computer storage medium storing instructions which, when executed by a device, cause the device to perform a method, the method comprising: identifying, by a controller of a device having a memory, a first logical address map of a plurality of logical address maps as active, wherein while the first logical address map is active the first logical address map is used by the controller to access data stored in the memory; and identifying, by the controller a second logical address map of the plurality of logical address maps as inactive [The rationale in the rejection of claim 1 is herein incorporated].
20. The non-transitory computer storage medium of claim 19, wherein the instructions are configured as a first component and a second component; wherein only one instance of the first component is allowed to run in the device at a time to modify a logical address map in the memory [Willman teaches “[0101] As discussed above, the invention creates and maintains an isolated memory by ensuring that untrusted code cannot use an address translation map that points to isolated memory. As further discussed above, since the isolation of a portion of memory depends on the address translation map not being modified in a way that would point to isolated memory, operations that affect the map are preferably performed by a trusted component in the trusted environment. FIGS. 7 and 8 show exemplary processes in which the trusted environment evaluates and controls changes to the map that arise out of the untrusted environment. In general, operations that affect the map--either changes to a map, or the activation of a new map--should be performed in the trusted environment, even when those operations arise out of the untrusted environment.”].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Belevich et al. (US 2005/0223186) in view of Willman et al. (US 2003/0200402) as applied in the rejection of claims 1, and further in view of Revanuru (US 20090198899).
2. The combination of Belevich and Willman teaches The device of claim 1, where Belevich teaches [translation maps A and B (fig. 11 and related text)] and Willman teaches [“With virtual addressing, as is known in the art, a virtual address facility such as the computer's memory management unit (MMU) uses a set of translation maps to convert a virtual address into a physical address. When a system supports virtual addressing, any memory location can be made accessible by editing the address translation maps to assign a virtual address to the desired physical memory location.” (par. 0003)] but does not expressly disclose wherein the controller is further configured to generate, in the memory, the first logical address map and the second logical address map of the plurality of logical address maps, wherein the second logical address map is identical to the first logical address map at a time of generation of the second logical address map; however, regarding these limitations, Revanuru teaches [“[0032] In one example, cache can be just a java.util.Map as far as the user is concerned. The Map derives its properties from the configuration. For example if the Map is configured to be replicated then all updates to the Map are propagated to other nodes in the cluster… [0202] In one example, servers that create the coherent replicated map using the following snippet form a group and keep the cache entries in sync. This means that each server in the cluster creates the coherent replicated cache type with the same name to join the group. Cluster members that do not create the cache locally are able to get the updates.”].
Belevich, Willman and Revanuru are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Belevich and Willman to have the second map be identical to the first map at a time of generation or replica as taught by Revanuru since doing so would provide the benefits of enhancing caching features such as replication.
Therefore, it would have been obvious to combine Belevich, Willman and Revanuru for the benefit of creating a storage system/method to obtain the invention as specified in claim 2.
Claims 8, 11-12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Belevich et al. (US 2005/0223186) in view of Willman et al. (US 2003/0200402) as applied in the rejection of claims 1, and further in view of Joshi et al. (US 20100036889).
8. The device of claim 1, wherein the controller is further configured to: receive, during a time period in which the first logical address map is identified as active, a first request to load from the memory a map for logical addresses; and provide, in response to the first request, the first logical address map [Belevich teaches [0043] Entire translation maps can be upgraded and then changed atomically using a similar approach. Referring to FIG. 10, a selection bit 168 of the block switching logic 142C determines whether translation map A or translation map B is applied to the external addresses. Updating a translation map can be achieved by identifying one of the translation maps (e.g., map A) as the active map and the other map (e.g., map B) as the inactive map, the inactive map is then updated in the background while the active map is in use. After the active translation map is updated, the selection bit can be switched to make translation map B the active translation map and translation map A the inactive map. The atomic switch between translation maps prevents a partially upgraded translation map from being used to identify an internal address.” where identifying the second map as active and applying a given translation map identified as active for a translation corresponds to loading the map. Willman additionally teaches “[0081] FIG. 4 shows an exemplary process for evaluating whether a new address translation map may be activated. The example of FIG. 4 assumes that a new address translation map is activated by writing a pointer to the map's base address into a defined storage location (e.g., storage location 201 shown in FIG. 2). However, it will be understood that the invention is not limited to the situation where address translation maps are activated in this manner, and that the process of FIG. 4 can be applied to any system that allows the currently-active address translation map to be replaced with another map.” Where the currently active map as indicated by storage location 201 is interpreted as loaded and where page tables are stored in RAM 132 (see figs. 1 and 2 and related text)] but the combination of Belevich and Willman does not expressly disclose the loading to a cache; however, regarding these limitations, Joshi teaches [“ Namespace database 240 is used to persistently store the primary namespace map for computer system 100 and contains all of the mapping information needed to correctly map filenames used by VMs 140 to filenames used by central storage unit 130. Cache memory unit 215 contains only a portion of the primary namespace map.” (par. 0025) “[0026] HFVL 210 is a software component that resides on an operating system for the server platform. HFVL 210 acts as a gateway between a file system driver running in the guest operating system of VMs 140 and central storage unit 130. It also interacts with RFVL 230 to implement the guest namespace virtualization and employs cache memory unit 215 to cache namespace maps as they are resolved by RFVL 230.”].
Belevich, Willman and Joshi are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Belevich and Willman to have the loading of the active map to a cache as taught by Joshi since doing so would provide the benefits of [“[0007] One or more embodiments of the invention provide a centralized way of managing virtual machines. By centrally managing virtual machines, overall CPU and memory usage is reduced and administration of programs that provide management services to virtual machines is simplified.”].
Therefore, it would have been obvious to combine Belevich, Willman and Joshi for the benefit of creating a storage system/method to obtain the invention as specified in claim 8.
11. The combination of Belevich and Willman teaches The device of claim 1, but does not expressly disclose wherein the controller comprises a plurality of processors, each having a cache; however, regarding these limitations [Joshi teaches “[0024] Each of server platforms 110 has conventional components of a server computer, and may be implemented as a cluster of multiple server computers. Each server platform has configured therein one or more virtual machines 140 that share hardware resources of the server platform, such as system memory 112, processor 114 and storage interface 116.” Where each server platform also comprises a cache 215 (fig. 2 and related text)].
Belevich, Willman and Joshi are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Belevich and Willman to have a plurality of processors, each having a cache as taught by Joshi since doing so would provide the benefits of [“[0007] One or more embodiments of the invention provide a centralized way of managing virtual machines. By centrally managing virtual machines, overall CPU and memory usage is reduced and administration of programs that provide management services to virtual machines is simplified.”].
Therefore, it would have been obvious to combine Belevich, Willman and Joshi for the benefit of creating a storage system/method to obtain the invention as specified in claim 11.
12. The combination of Belevich and Willman teaches The device of claim 1, wherein the memory comprises non-volatile storage media; and [Belevich teaches non-volatile memory device 140 including and programmable non-volatile memory 144 (fig. 5 and related text)] the first logical address map is configured to map logical addresses defined in one or more namespaces to logical addresses defined in a capacity of the non-volatile storage media [Belevich teaches “[0031] As described above, the device-level translation rules are changeable. That is, the mapping of the external addresses to the internal addresses can be changed to accomplish a desired result. FIG. 7A is a graphical depiction of the translation map 150 from FIG. 6A after the translation rules have been changed. In the example of FIG. 7A, the external address space of 0x00000-0x0ffff now maps to internal address 1, the external address space 0x10000-0x1ffff now maps to internal address 3, the external address space 0x20000-0x2ffff now maps to internal address N, the external address space 0x30000-0x3ffff now maps to internal address 0, and the external address space 0xN0000-0xNffff now maps to internal address K, where internal address K is some internal address between internal addresses 3 and N.” thus teaching external spaces mapping to a capacity of the non-volatile memory 144] but the combination does not expressly refer to the one or more spaces as one or more namespaces; however, regarding these limitations, Joshi teaches [“A cache memory unit 215 is provided to support namespace mapping that is carried out by the server platform and a namespace database 240 is provided to support namespace mapping that is carried out by switching layer computer 220. Namespace database 240 is used to persistently store the primary namespace map for computer system 100 and contains all of the mapping information needed to correctly map filenames used by VMs 140 to filenames used by central storage unit 130. Cache memory unit 215 contains only a portion of the primary namespace map.” (par. 0025)].
Belevich, Willman and Joshi are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Belevich and Willman to have the one or more spaces as one or more namespaces as taught by Joshi since doing so would provide the benefits of [“[0007] One or more embodiments of the invention provide a centralized way of managing virtual machines. By centrally managing virtual machines, overall CPU and memory usage is reduced and administration of programs that provide management services to virtual machines is simplified.”].
Therefore, it would have been obvious to combine Belevich, Willman and Joshi for the benefit of creating a storage system/method to obtain the invention as specified in claim 12.
18. The method of claim 15, further comprising: receiving, during a time period in which the first logical address map is identified as active, a first request to load from the memory a map for logical addresses; and providing, in response to the first request, the first logical address map to a cache in the device [The rationale in the rejection of claim 8 is herein incorporated].
Claims 9-10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Belevich et al. (US 2005/0223186) in view of Willman et al. (US 2003/0200402) and Joshi et al. (US 20100036889) as applied in the rejection of claim 8 above, and further in view of Revanuru (US 20090198899).
9. The combination of Belevich, Willman and Joshi teaches The device of claim 8, wherein the controller is further configured to: communicate, in response to the second logical address map being identified as active, with the cache to synchronize the first logical address map loaded in the cache with the second logical address map [Belevich teaches “[0043] Entire translation maps can be upgraded and then changed atomically using a similar approach. Referring to FIG. 10, a selection bit 168 of the block switching logic 142C determines whether translation map A or translation map B is applied to the external addresses. Updating a translation map can be achieved by identifying one of the translation maps (e.g., map A) as the active map and the other map (e.g., map B) as the inactive map, the inactive map is then updated in the background while the active map is in use. After the active translation map is updated, the selection bit can be switched to make translation map B the active translation map and translation map A the inactive map.” Joshi teaches “Dynamic virtualization is achieved by updating the namespace map in namespace database 240 and invalidating the namespace maps stored in cache memory unit 215.” (par. 0028)] but the combination does not expressly disclose to synchronize the first map… with the second map; however, regarding these limitations, Revanuru teaches [“[0032] In one example, cache can be just a java.util.Map as far as the user is concerned. The Map derives its properties from the configuration. For example if the Map is configured to be replicated then all updates to the Map are propagated to other nodes in the cluster… [0202] In one example, servers that create the coherent replicated map using the following snippet form a group and keep the cache entries in sync. This means that each server in the cluster creates the coherent replicated cache type with the same name to join the group. Cluster members that do not create the cache locally are able to get the updates.”].
Belevich, Willman, Joahi and Revanuru are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Belevich, Willman and Joshi to to synchronize the first map… with the second map as taught by Revanuru since doing so would provide the benefits of enhancing caching features such as replication.
Therefore, it would have been obvious to combine Belevich, Willman, Joshi and Revanuru for the benefit of creating a storage system/method to obtain the invention as specified in claim 9.
10. The device of claim 9, wherein the cache is configured in a core of a processor of the controller [Willman teaches cache 132 in computer 110 (figs. 1 and 2 and related text) “ RAM 132 typically contains data and/or program modules that are immediately accessible to and/or presently being operated on by processing unit 120. By way of example, and not limitation, FIG. 1 illustrates operating system 134, application programs 135, other program modules 136, and program data 137.” (par. 0041). Joshi teaches caches 215 in server platforms (fig. 2 and related text) where “[0024] Each of server platforms 110 has conventional components of a server computer, and may be implemented as a cluster of multiple server computers. Each server platform has configured therein one or more virtual machines 140 that share hardware resources of the server platform, such as system memory 112, processor 114 and storage interface 116.”].
17. The method of claim 16, further comprising communicating, in response to the second logical address map being identified as active, with a cache of the device to synchronize the first logical address map loaded in the cache with the second logical address map [The rationale in the rejection of claim 9 is herein incorporated].
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Belevich et al. (US 2005/0223186) in view of Willman et al. (US 2003/0200402) as applied in the rejection of claims 1, and further in view of IM (US 20120311238 A1).
13. The device of claim 1, wherein the memory further includes a volatile random access memory; and the first logical address map and the second logical address are stored in the volatile random access memory [Belevich teaches translation map A and translation map B (fig. 11 and related text). Willman teaches “[0049] In system 200, page directory 202 contains an array of entries. Each entry may contain a pointer to (i.e., physical base addresses of) a page table, such as page tables 204(1), 204(2), and 204(3). Each page table, in turn, contains an array of entries that may contain pointers to the base addresses of pages (e.g., pages 206(1), 206(2), 206(3), and 206(4)). Pages are fixed-length portions of RAM 132. It should be noted that the page directory and page tables themselves are also typically stored in pages of RAM. Typically, the system divides RAM 132 into pages, and assigns pages to store any type of data, whether the data is program data, or address translation mapping data, or any other kind of data. Thus, in system 200, the difference between page directory 202, page tables 204(1) through 204(3), and pages 206(1) through 206(4) has to do with the function of the data stored in these respective structures, rather than any structural or physical property of the memory--i.e., pages 206(1) through 206(4) may store program data, and the page directory and page tables store various levels of pointers leading to the program data. It should also be noted that, since page tables and page directories need to be read, and usually modified, during the operation of the program, the page tables may contain mappings leading recursively to themselves, or to the page directory, so that the page directory/tables can be read and/or written by virtual address.”] but the combination of Belevich and Willman does not expressly disclose the first logical address map and the second logical address are stored in the volatile random access memory; however, regarding these limitations, IM teaches [“[0006] The first mapping table may be stored in the first memory chip and the second mapping table may be stored in the second memory chip. In this example, the control unit may include a RAM configured to store the first mapping table and the second mapping table; a processor configured to update the first mapping table and the second mapping table both stored within the RAM; and a memory controller unit connected to the first memory chip and the second memory chip.”].
Belevich, Willman and IM are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Belevich and Willman to have the first logical address map and the second logical address are stored in the volatile random access memory as taught by IM since doing so would provide the benefits of facilitating access and updating of the mapping tables.
Therefore, it would have been obvious to combine Belevich, Willman and IM for the benefit of creating a storage system/method to obtain the invention as specified in claim 13
CLOSING COMMENTS
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
a(2) ALLOWABLE SUBJECT MATTER
Per the instant office action, claim 14 would objected to (if the double patenting rejections above are overcome) as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if the double patenting rejections above are overcome.
14. The device of claim 13, wherein the controller is configured with firmware having a first component and a second component; wherein only one instance of the first component is allowed to run in the device at a time to modify a logical address map in the volatile random access memory that is not identified as active; and wherein multiple instances of the second components are allowed to run concurrently in the device but not allowed to modify a logical address map in the volatile random access memory.
b. DIRECTION OF FUTURE CORRESPONDENCES
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January 27, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135