DETAILED ACTION
This action is responsive to the Applicant's amendments filed on 07/28/2026. Claims 1-20 remain pending in the application. Claims 1-7, 9-10, 12-18, and 20 have been amended. Any examiner's note, objection, and rejection not repeated is withdrawn due to Applicant's amendment.
Response to Arguments
Applicants’ arguments filed 07/28/2026 have been fully considered but persuasive. Applicant's arguments are summarized below:
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of non-statutory obviousness-type double
patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,191,882.
Claim 1 of the present application teaches "A decoder, comprising: a check node updating circuit comprising first updating circuits of a levels, wherein the first updating circuit of each level is connected sequentially, the first updating circuit of each level except the first updating circuit of a first level sequentially receive variable node messages corresponding to each column of a check matrix, and sequentially calculate the received variable node messages with messages in the first updating circuit of a previous level, and obtain to obtain check node messages corresponding to different layers of the check matrix in the first updating circuits of different levels in the first updating circuits of a levels, wherein the first updating circuit of the a-th level is connected with the first updating circuit of the first level; and a variable node updating circuit connected with the check node updating circuit, the variable node updating circuit comprises second updating circuits of a levels, wherein the second updating circuit of each level is connected sequentially, the second updating circuit of the a-th level sequentially receive the variable node messages corresponding to each column of the check matrix, the second updating circuit of each level except the second updating circuit of the a-th level sequentially receive the check node messages corresponding to each layer of the check matrix, and update messages of the second updating circuit of a next level and perform calculation to obtain corresponding intermediate calculation values, and the second updating circuit of each level except the second updating circuit of the a-th level sequentially receive the check node messages corresponding to each layer of the check matrix, and sequentially calculate the received check node messages with the intermediate calculation values of the second updating circuit of the next level, to obtain the variable node messages corresponding to different columns of the check matrix in the second updating circuits of different levels in the second updating circuits of a levels, wherein the second updating circuit of the a-th level is connected with the second updating circuit of the first level". Whereas claim 1 of U.S. PN: 12,191,882 teaches "A decoder, wherein a check matrix corresponding to a frame of code words comprises a sub-matrices, a plurality of sub-matrices located in the same row in the check matrix constitute a layer of the check matrix, and a plurality of sub-matrices located in the same column constitute a column of the check matrix, the decoder comprising: a check node updating circuit that comprises first updating units of a levels, wherein the first updating unit of each level is connected sequentially; and a variable node updating circuit that is connected with the check node updating circuit, the variable node updating circuit comprises second updating units of a levels, wherein the second updating unit of each level is connected sequentially; wherein, in a first time period, the check node updating circuit is configured to cause: the first updating unit of each level except the first updating unit of a first level sequentially receive variable node messages corresponding to each column of the check matrix, and sequentially calculate the received variable node messages with messages in the first updating unit of a previous level, to obtain the check node messages corresponding to different layers of the check matrix in the first updating units of different levels in the first updating units of a levels; in the first time period, the variable node updating circuit is configured to cause: the second updating unit of the a- th level sequentially receive the variable node messages corresponding to each column of the check matrix, and the second updating unit of each level except the second updating unit of the a-th level sequentially receive the messages of the second updating unit of a next level and performing calculation, to obtain corresponding intermediate calculation values in the second updating units of different levels in the second updating units of a levels; and in a second time period after the first time period, the variable node updating circuit is configured to cause: the second updating unit of each level except the second updating unit of the a-th level sequentially receive the check node messages corresponding to each layer of the check matrix, and sequentially calculate the received check node messages with the intermediate calculation values of the second updating unit of the next level, to obtain the variable node messages corresponding to different columns of the check matrix in the second updating units of different levels in the second updating units of a levels".
The examiner would like to point out that claim 1 of the present application is substantially the same of claim 1 of U.S. Patent No. 12,191,882. One is just an embodiment of the other and the claims are obvious variations of each other and not patentably distinct.
"A latter patent claim is not patentably distinct from an earlier patent claim if the latter
claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,
225 USPQ at 651 (affirming a holding of obvious-type double patenting because the
claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obvious-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). ELI LILLY AND COMPANYv BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claim 10 of the present application teaches "a memory system comprising: a memory device; and a decoder coupled to the memory device and configured to decode the data read from the memory device; wherein the decoder comprises: a check node updating circuit comprising first updating units updating circuits of a levels, wherein the first updating circuit of each level is connected sequentially, the first updating circuit of each level except the first updating circuit of a first level sequentially receive variable node messages corresponding to each column of a check matrix, and sequentially calculate the received variable node messages with messages in the first updating circuit of a previous level, and obtain to obtain check node messages corresponding to different layers of the check matrix in the first updating circuits of different levels in the first updating circuits of a levels, wherein the first updating circuit of the a-th level is connected with the first updating circuit of the first level; and a variable node updating circuit connected with the check node updating circuit, the variable node updating circuit comprises second updating circuits of a levels, wherein the second updating circuit of each level is connected sequentially, the second updating circuit of the a-th level sequentially receive the variable node messages corresponding to each column of the check matrix, the second updating circuit of each level except the second updating circuit of the a-th level sequentially receive the check node messages corresponding to each layer of the check matrix, and update messages of the second updating circuit of a next level and perform calculation to obtain corresponding intermediate calculation values, and the second updating circuit of each level except the second updating circuit of the a-th level sequentially receive the check node messages corresponding to each layer of the check matrix, and sequentially calculate the received check node messages with the intermediate calculation values of the second updating circuit of the next level, to obtain the variable node messages corresponding to different columns of the check matrix in the second updating circuits of different levels in the second updating circuits of a levels, wherein the second updating circuit of the a-th level is connected with the second updating circuit of the first level. Whereas claim 11 of U.S. PN: 12,191,882 teaches "A memory system comprising: a memory controller; and a memory device coupled to the memory controller; wherein the memory controller comprises a decoder, wherein a check matrix corresponding to a frame of code words comprises a*a sub-matrices, a plurality of sub-matrices located in the same row in the check matrix constitute a layer of the check matrix, and a plurality of sub-matrices located in the same column constitute a column of the check matrix, the decoder comprising: a check node updating circuit that comprises first updating units of a levels, wherein the first updating unit of each level is connected sequentially; and a variable node updating circuit that is connected with the check node updating circuit, the variable node updating circuit comprises second updating units of a levels, wherein the second updating unit of each level is connected sequentially; wherein, in a first time period, the check node updating circuit is configured to cause: the first updating unit of each level except the first updating unit of a first level sequentially receive variable node messages corresponding to each column of the check matrix, and sequentially calculate the received variable node messages with messages in the first updating unit of a previous level, to obtain the check node messages corresponding to different layers of the check matrix in the first updating units of different levels in the first updating units of a levels; in the first time period, the variable node updating circuit is configured to cause: the second updating unit of the a-th level sequentially receive the variable node messages corresponding to each column of the check matrix, and the second updating unit of each level except the second updating unit of the a-th level sequentially receive the messages of the second updating unit of a next level and performing calculation, to obtain corresponding intermediate calculation values in the second updating units of different levels in the second updating units of a levels; and in a second time period after the first time period, the variable node updating circuit is configured to cause: the second updating unit of each level except the second updating unit of the a-th level sequentially receive the check node messages corresponding to each layer of the check matrix, and sequentially calculate the received check node messages with the intermediate calculation values of the second updating unit of the next level, to obtain the variable node messages corresponding to different columns of the check matrix in the second updating units of different levels in the second updating units of a levels".
The examiner would like to point out that claim 10 of the present application is substantially the same of claim 11 of U.S. Patent No. 12,191,882. One is just an embodiment of the other and the claims are obvious variations of each other and not patentably distinct.
"A latter patent claim is not patentably distinct from an earlier patent claim if the latter
claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,
225 USPQ at 651 (affirming a holding of obvious-type double patenting because the
claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obvious-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). ELI LILLY AND COMPANYv BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Other parallel dependent claims have corresponding issues with the dependent claims of U.S. Patent No. 12,191,882 are also rejected under a non-statutory obviousness-type double patenting.
Allowable Subject Matter
Claims 1-20 would be allowable if the applicant files Terminal Disclaimer to overcome the rejection(s) under obvious-type non-statutory double patenting, set forth in this Office action.
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ESAW T ABRAHAM whose telephone number is (571)272-3812. The examiner can normally be reached on 8AM-4:30PM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
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/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112
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