FINAL OFFICE ACTION
Status of the Claims
Claims 1-25 are rejected under 35 U.S.C. 103
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11, 13-14, 16-18, and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Hughes et al. (U.S. Publication No. 2025/0292349 A1), hereinafter referred to as Hughes, in view of Chen et al. (U.S. Publication No. 2025/0209027 A1), hereinafter referred to as Chen.
Regarding Claim 1 Hughes teaches:
An apparatus comprising:
a plurality of processors including a first processor and a second processor; ([0044]; regarding, “The computing system 100 includes a processing subsystem 101 having one or more processor(s) 102”);
and a plurality of interconnects coupled to the plurality of processors, ([0048]; regarding, “the one or more parallel processor(s) 112, memory hub 105, processor(s) 102, and I/O hub 107 can be integrated into a system on chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system in package (SIP) configuration. In one embodiment at least a portion of the components of the computing system 100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.”)
Hughes fails to explicitly disclose but Chen teaches:
wherein the plurality of interconnects further includes a plurality of principle interconnects and a plurality of redundant interconnects, wherein the plurality of interconnects is to transmit signals between the first processor and the second processor using one or more encoding schemes based on an indication from one or more logics associated with the plurality of processors, ([0045]; regarding, “Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any compatible combination of, the examples described below.”; [0046]; regarding, “he first plurality of interconnect sections are part of a first integrated circuit (IC). The first plurality of interconnect sections are switchably coupled together through demultiplexer circuitry that has a first set of signal inputs, wherein the first plurality of interconnect sections include one or more redundant interconnect sections. The control circuitry controls the demultiplexer circuitry to redirect one or more of the signal inputs away from one or more faulty interconnect sections from the first plurality of interconnect sections to at least one of the one or more redundant interconnect sections. The first plurality of interconnect sections are to be coupled to complementary interconnect sections from a second IC.”);
wherein the one or more encoding schemes includes a first encoding scheme and a second encoding scheme, ([0019]; regarding, “…replacement scheme can fix a single failing region, i.e., a single unit for each class in a group, but if there are multiple fault regions that are spread out, another approach may be employed to complement the spatial redundancy scheme.”; [0022]; regarding, “Depending on the utilized scheme, for example, if separate multilane channels are used as is depicted, the complementary contact pairs may be divided in order to implement the separate multilane channels, or alternatively, separate interconnect tiles could be used for each multilane channel. As with many aspects of this disclosure, particular implementations will depend on specific design limitations and objectives.”);
wherein the first encoding scheme applies signals over some but not all of the plurality of redundant interconnects based on a first logic level of the indication, and wherein the second encoding scheme applies signals over the plurality of principle interconnects and the plurality of redundant interconnects based on a second logic level of the indication, ([0008]; regarding, “Disclosed are reliability solutions for multi-chip interconnect systems such as with HBI based interconnect schemes.”; [0019]; regarding, “The units from each class are coupled to an associated demultiplexer circuit 260, which has a set of 28 incoming signal inputs (e.g., data, ECC, or other), as shown, and channels the signal input pathways through selected units, bypassing any previously identified faulty unit, and directing the signal input paths out through multiplexer circuit 275. For example, the A chain, which includes units qA8, qA9, qA10, qA11, qA3, qaA2, qA1, and qA0 (redundant unit), is coupled to demultiplexer circuit 260A to receive signals A0-A27. Should any one of the units be faulty, the signal paths, beginning with the paths aligned with the faulty unit, are redirected, shifted rightward in this implementation, thereby effectively replacing the faulty unit with the redundant unit. For example, if the 4th unit (qA11) is bad, the signal paths A0-A11 are routed to the first three units (qA8-qA10), while signal paths A12-A27 are redirected through the last four units (qA3-qA0), thereby bypassing the faulty qA11 unit.”; [0065]; regarding, “A first portion of the complementary contact pairs are used as channels for the interconnect units, and a second portion of the complementary contact pairs are used to supply power from the first IC to the second IC. The plurality of interconnect units include a multiplicity of interconnect unit chains each including signal line and redundant interconnect units, wherein for each chain, a detected faulty one of the signal line interconnect units may be replaced in the chain with at least one of the redundant interconnect units.”);
and wherein the first logic level is different from the second logic level. ([0024]; regarding, “In operation… the data flit and ECC code are conveyed to the SR encode circuit 315A, which may implement circuitry similar to the multiplexer system circuitry of FIG. 2D, to configure the particular interconnect paths used for transmitting the flit and ECC signals.”; [0026]; regarding, “Once any defective contact paths are identified and bypassed using the redundant interconnects… the verified pathways are then stored… in the SR circuitry 315A itself, so that the updated paths may be used for normal communications operations.”; [0027]; regarding, “When in a normal operational mode, the flit data is conveyed through the SR encode circuitry (pathway network… Depending on whether defective units for the TxA_Flit and/or TxA_Ecc lines are identified or not, the TxA_RR lines will be, or will not be, used as needed.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Hughes with the teachings of Chen. Doing so could limit the amount of overhead when replacing faulty interconnects (Chen, [0008]).
Regarding Claim 2 Hughes in view of Chen teaches the apparatus of claim 1 as referenced above. Hughes in view of Chen further teaches:
wherein the one of more logics are an operating system that execute on the plurality of processors. (Hughes, [0204]; regarding, “The programmable network interface 1210 can include a system on a chip (SoC 1220) that executes an operating system via multiple processor cores 1222.”).
Regarding Claim 3 Hughes in view of Chen teaches the apparatus of claim 1 as referenced above. Hughes in view of Chen further teaches:
wherein the one or more logics, based on the first logic level of the indication, reconfigures the plurality of redundant interconnects to reclaim a logical configuration of the plurality of processors, and wherein the logical configuration is one of a fully-connected configuration, a fat-tree configuration, or a mesh configuration. (Hughes, [0233]; regarding, “A ring or mesh based interconnect 1512 may be used to couple the internal components of the processor 1500. However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art...”).
Regarding Claim 4 Hughes in view of Chen teaches the apparatus of claim 1 as referenced above. Hughes in view of Chen further teaches:
wherein the first logic level indicates presence of a fault in at least one processor of the plurality of processors. (Chen, [0026]; regarding, “Once any defective contact paths are identified and bypassed using the redundant interconnects… the verified pathways are then stored… in the SR circuitry 315A itself, so that the updated paths may be used for normal communications operations.”; [0027]; regarding, “When in a normal operational mode, the flit data is conveyed through the SR encode circuitry (pathway network… Depending on whether defective units for the TxA_Flit and/or TxA_Ecc lines are identified or not, the TxA_RR lines will be, or will not be, used as needed.”).
Regarding Claim 5 Hughes in view of Chen teaches the apparatus of claim 1 as referenced above. Hughes in view of Chen further teaches:
wherein the second logic level indicates absence of a fault in the plurality of processors. (Chen, [0024]; regarding, “In operation… the data flit and ECC code are conveyed to the SR encode circuit 315A, which may implement circuitry similar to the multiplexer system circuitry of FIG. 2D, to configure the particular interconnect paths used for transmitting the flit and ECC signals.”; [0027]; regarding, “When in a normal operational mode, the flit data is conveyed through the SR encode circuitry (pathway network… Depending on whether defective units for the TxA_Flit and/or TxA_Ecc lines are identified or not, the TxA_RR lines will be, or will not be, used as needed.”).
Regarding Claim 6 Hughes in view of Chen teaches the apparatus of claim 1 as referenced above. Hughes in view of Chen further teaches:
wherein the plurality of processors is a plurality of dies. (Hughes, [0323]; regarding, “Each chiplet can be fabricated as separate semiconductor die and coupled with a base die that is embedded within or coupled with the substrate 2580.”).
Regarding Claim 7 Hughes in view of Chen teaches the apparatus of claim 6 as referenced above. Hughes in view of Chen further teaches:
wherein the plurality of dies is coupled in a fully-connected configuration, a fat-tree configuration, or a mesh configuration. (Hughes, [0233]; regarding, “A ring or mesh based interconnect 1512 may be used to couple the internal components of the processor 1500. However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art.”)
Regarding Claim 8 Hughes in view of Chen teaches the apparatus of claim 1 as referenced above. Hughes in view of Chen further teaches:
wherein the plurality of processors is one or more processor cores. (Hughes, [0229]; regarding, “The processor 1500 may have one or more processor cores 1502A-1502N”).
Regarding Claim 9 Hughes in view of Chen teaches the apparatus of claim 8 as referenced above. Hughes in view of Chen further teaches:
wherein the one or more processor cores is coupled in a fully-connected configuration, a fat-tree configuration, or a mesh configuration. (Hughes, [0233]; regarding, “A ring or mesh based interconnect 1512 may be used to couple the internal components of the processor 1500. However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art.”).
Regarding Claim 10 Hughes in view of Chen teaches the apparatus of claim 1 as referenced above. Hughes in view of Chen further teaches:
wherein the plurality of processors is a plurality of chips, each with multiple processor cores. ([0235]; regarding, “the processor 1500 can be implemented on one or more chips or chiplets, or as an SoC integrated circuit having the illustrated components, in addition to other components. The SoC integrated circuit may be implemented using multiple chiplets.”; [0229]; regarding, “The processor 1500 may have one or more processor cores 1502A-1502N”).
Regarding Claim 11 Hughes in view of Chen teaches the apparatus of claim 10 as referenced above. Hughes in view of Chen further teaches:
wherein the plurality of chips is coupled in a fully-connected configuration, a fat-tree configuration, or a mesh configuration. (Hughes, [0233]; regarding, “A ring or mesh based interconnect 1512 may be used to couple the internal components of the processor 1500. However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art.”).
Regarding Claim 13, Hughes in view of Chen teaches:
one or more encoders to transmit a first set of signals on some but not all of plurality of redundant interconnects based on a first logic level of an indication from one or more logic circuits, and to transmit a second set of signals on a set of principle interconnects and the plurality of redundant interconnects based on a second logic level of the indication, (Chen, [0008]; regarding, “Disclosed are reliability solutions for multi-chip interconnect systems such as with HBI based interconnect schemes.”; [0019]; regarding, “The units from each class are coupled to an associated demultiplexer circuit 260, which has a set of 28 incoming signal inputs (e.g., data, ECC, or other), as shown, and channels the signal input pathways through selected units, bypassing any previously identified faulty unit, and directing the signal input paths out through multiplexer circuit 275. For example, the A chain, which includes units qA8, qA9, qA10, qA11, qA3, qaA2, qA1, and qA0 (redundant unit), is coupled to demultiplexer circuit 260A to receive signals A0-A27. Should any one of the units be faulty, the signal paths, beginning with the paths aligned with the faulty unit, are redirected, shifted rightward in this implementation, thereby effectively replacing the faulty unit with the redundant unit. For example, if the 4th unit (qA11) is bad, the signal paths A0-A11 are routed to the first three units (qA8-qA10), while signal paths A12-A27 are redirected through the last four units (qA3-qA0), thereby bypassing the faulty qA11 unit.”; [0065]; regarding, “A first portion of the complementary contact pairs are used as channels for the interconnect units, and a second portion of the complementary contact pairs are used to supply power from the first IC to the second IC. The plurality of interconnect units include a multiplicity of interconnect unit chains each including signal line and redundant interconnect units, wherein for each chain, a detected faulty one of the signal line interconnect units may be replaced in the chain with at least one of the redundant interconnect units.”);
wherein the second logic level is different than the first logic level, (Chen, [0024]; regarding, “In operation… the data flit and ECC code are conveyed to the SR encode circuit 315A, which may implement circuitry similar to the multiplexer system circuitry of FIG. 2D, to configure the particular interconnect paths used for transmitting the flit and ECC signals.”; [0026]; regarding, “Once any defective contact paths are identified and bypassed using the redundant interconnects… the verified pathways are then stored… in the SR circuitry 315A itself, so that the updated paths may be used for normal communications operations.”; [0027]; regarding, “When in a normal operational mode, the flit data is conveyed through the SR encode circuitry (pathway network… Depending on whether defective units for the TxA_Flit and/or TxA_Ecc lines are identified or not, the TxA_RR lines will be, or will not be, used as needed.”).
wherein the set of principle interconnects and the plurality of redundant interconnects are connected between a first processor and a second processor. (Hughes, [0048]; regarding, “the one or more parallel processor(s) 112, memory hub 105, processor(s) 102, and I/O hub 107 can be integrated into a system on chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system in package (SIP) configuration. In one embodiment at least a portion of the components of the computing system 100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.”; [0081]; regarding, “The various components can communicate via an interconnect fabric 290… the interconnect fabric 290 may be a separate, high-speed network fabric layer upon which each component of the graphics multiprocessor 235 is stacked. The components of the graphics multiprocessor 235 can also communicate with remote components via the interconnect fabric 290.”).
Regarding Claim 14 Hughes in view of Chen teaches the apparatus of claim 13 as referenced above. Hughes in view of Chen further teaches:
wherein the first logic level indicates presence of a fault in at least one of the first processor or the second processor, and wherein the second logic level indicates absence of a fault in the first processor and the second processor. (Chen, [0024]; regarding, “In operation… the data flit and ECC code are conveyed to the SR encode circuit 315A, which may implement circuitry similar to the multiplexer system circuitry of FIG. 2D, to configure the particular interconnect paths used for transmitting the flit and ECC signals.”; [0026]; regarding, “Once any defective contact paths are identified and bypassed using the redundant interconnects… the verified pathways are then stored… in the SR circuitry 315A itself, so that the updated paths may be used for normal communications operations.”; [0027]; regarding, “When in a normal operational mode, the flit data is conveyed through the SR encode circuitry (pathway network… Depending on whether defective units for the TxA_Flit and/or TxA_Ecc lines are identified or not, the TxA_RR lines will be, or will not be, used as needed.”).
Regarding Claim 16, Hughes in view of Chen teaches:
A wafer-level assembly of chiplets comprising:
a plurality of groups of chiplets including a first group of chiplets, and a second group of chiplets, wherein the first group of chiplets is organized as a first fully-connected configuration, and wherein the second group of chiplets is organized as a second fully-connected configuration; (Hughes, [0048]; regarding, “the one or more parallel processor(s) 112, memory hub 105, processor(s) 102, and I/O hub 107 can be integrated into a system on chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system in package (SIP) configuration.”; [0216]; regarding, “The processing system 1400 may be a processing system having components that correspond with those of FIG. 1. For example, in different configurations, processor(s) 1402 or processor cores 1407 may correspond with processor(s) 102 of FIG. 1.”; [0229]; regarding, “processor 1500, which may be a variant of one of the processor(s) 1402 and may be used in place of one of those. Therefore, the disclosure of any features in combination with the processor 1500 herein also discloses a corresponding combination with the processor(s) 1402 but is not limited to such. The processor 1500 may have one or more processor cores 1502A-1502N”; [0235]; regarding, “the processor 1500 can be implemented on one or more chips or chiplets, or as an SoC integrated circuit having the illustrated components, in addition to other components. The SoC integrated circuit may be implemented using multiple chiplets.”; [0319]; regarding, “A graphics processing unit, parallel processor, and/or compute accelerator as described herein can be composed from diverse silicon chiplets that are separately manufactured. In this context, a chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device. Additionally, the chiplets can be integrated into a base die or base chiplet using active interposer technology.”);
and a plurality of interconnects including a first set of interconnects and a second set of interconnects, wherein the first set of interconnects couples a first chiplet of the first group of chiplets with a first chiplet of the second group of chiplets, wherein the second set of interconnects couples a second chiplet of the first group of chiplets with a second chiplet of the second group of chiplets, (Hughes, [0320]; regarding, “a package assembly 2590 can include fewer or greater number of components and chiplets that are interconnected by an interconnect fabric 2585 or a bridge structure 2587. The bridge structure 2587 may be used to facilitate a point-to-point interconnect between, for example, a logic or I/O chiplet 2574 and memory chiplets 2575.”; [0321]; regarding, “The interconnect fabric 2585 may be an NoC interconnect or another form of packet switched fabric that switches data packets between components of the package assembly. For complex assemblies, the interconnect fabric 2585 may be a dedicated chiplet enables communication between the various hardware logic of the package assembly 2590.”);
wherein the plurality of interconnects is arranged in a mesh configuration, (Hughes, [0233]; regarding, “A ring or mesh based interconnect 1512 may be used to couple the internal components of the processor 1500.”);
wherein the first set of interconnects includes a first set of principle interconnects and a first set of redundant interconnects, wherein the second set of interconnects includes a second set of principle interconnects and a second set of redundant interconnects, (Chen, [0045]; regarding, “Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any compatible combination of, the examples described below.”; [0046]; regarding, “he first plurality of interconnect sections are part of a first integrated circuit (IC). The first plurality of interconnect sections are switchably coupled together through demultiplexer circuitry that has a first set of signal inputs, wherein the first plurality of interconnect sections include one or more redundant interconnect sections. The control circuitry controls the demultiplexer circuitry to redirect one or more of the signal inputs away from one or more faulty interconnect sections from the first plurality of interconnect sections to at least one of the one or more redundant interconnect sections. The first plurality of interconnect sections are to be coupled to complementary interconnect sections from a second IC.”);
wherein the plurality of interconnects is to transmit signals between the first chiplet of the first group of chiplets and the first chiplet of the second group of chiplets using one or more encoding schemes based on an indication from one or more logics associated with the plurality of groups of chiplets, (Chen, [0031]; regarding, “Multiprocessor system 400 is an interfaced system and includes a plurality of processors including a first processor 470 and a second processor 480 coupled via an interface 450 such as a point-to-point (P-P) interconnect, a fabric, and/or bus that may be implemented using spatially redundant interconnect systems”; [0024]; regarding, “In operation, a flit of data…to be transmitted to IC B is provided to the ECC generation circuit 310A, which processes the data bits… to generate an ECC code (TxA_Ecc) for the flit. From here, the data flit and ECC code are conveyed to the SR encode circuit 315A, which may implement circuitry similar to the multiplexer system circuitry of FIG. 2D, to configure the particular interconnect paths used for transmitting the flit and ECC signals.”);
wherein the one or more encoding schemes includes a first encoding scheme and a second encoding scheme, (Chen, [0019]; regarding, “…replacement scheme can fix a single failing region, i.e., a single unit for each class in a group, but if there are multiple fault regions that are spread out, another approach may be employed to complement the spatial redundancy scheme.”; [0022]; regarding, “Depending on the utilized scheme, for example, if separate multilane channels are used as is depicted, the complementary contact pairs may be divided in order to implement the separate multilane channels, or alternatively, separate interconnect tiles could be used for each multilane channel. As with many aspects of this disclosure, particular implementations will depend on specific design limitations and objectives.”);
wherein the first encoding scheme applies signals over some but not all of the first and second sets of redundant interconnects based on a first logic level of the indication, and wherein the second encoding scheme applies signals over the first and second sets of principle interconnects and the first and second sets of redundant interconnects based on a second logic level of the indication, (Chen, [0008]; regarding, “Disclosed are reliability solutions for multi-chip interconnect systems such as with HBI based interconnect schemes.”; [0019]; regarding, “The units from each class are coupled to an associated demultiplexer circuit 260, which has a set of 28 incoming signal inputs (e.g., data, ECC, or other), as shown, and channels the signal input pathways through selected units, bypassing any previously identified faulty unit, and directing the signal input paths out through multiplexer circuit 275. For example, the A chain, which includes units qA8, qA9, qA10, qA11, qA3, qaA2, qA1, and qA0 (redundant unit), is coupled to demultiplexer circuit 260A to receive signals A0-A27. Should any one of the units be faulty, the signal paths, beginning with the paths aligned with the faulty unit, are redirected, shifted rightward in this implementation, thereby effectively replacing the faulty unit with the redundant unit. For example, if the 4th unit (qA11) is bad, the signal paths A0-A11 are routed to the first three units (qA8-qA10), while signal paths A12-A27 are redirected through the last four units (qA3-qA0), thereby bypassing the faulty qA11 unit.”; [0065]; regarding, “A first portion of the complementary contact pairs are used as channels for the interconnect units, and a second portion of the complementary contact pairs are used to supply power from the first IC to the second IC. The plurality of interconnect units include a multiplicity of interconnect unit chains each including signal line and redundant interconnect units, wherein for each chain, a detected faulty one of the signal line interconnect units may be replaced in the chain with at least one of the redundant interconnect units.”);
and wherein the first logic level is different from the second logic level. (Chen, [0024]; regarding, “In operation… the data flit and ECC code are conveyed to the SR encode circuit 315A, which may implement circuitry similar to the multiplexer system circuitry of FIG. 2D, to configure the particular interconnect paths used for transmitting the flit and ECC signals.”; [0026]; regarding, “Once any defective contact paths are identified and bypassed using the redundant interconnects… the verified pathways are then stored… in the SR circuitry 315A itself, so that the updated paths may be used for normal communications operations.”; [0027]; regarding, “When in a normal operational mode, the flit data is conveyed through the SR encode circuitry (pathway network… Depending on whether defective units for the TxA_Flit and/or TxA_Ecc lines are identified or not, the TxA_RR lines will be, or will not be, used as needed.”).
Regarding Claim 17 Hughes in view of Chen teaches the assembly of claim 16 as referenced above. Hughes in view of Chen further teaches:
a substrate, wherein the plurality of groups of chiplets is on the substrate, and wherein the substrate includes a redistribution layer. (Hughes, [0319]; regarding, “a package assembly 2590 for an integrated circuit that includes multiple units of hardware logic chiplets connected to a substrate 2580”; [0337]; regarding, “the chiplets have configurable power management policies and mechanisms to optimize power consumption and thermal characteristics across the chiplets.”).
Regarding Claim 18 Hughes in view of Chen teaches the assembly of claim 17 as referenced above. Hughes in view of Chen further teaches:
wherein the plurality of interconnects is in the substrate, wherein the substrate includes a bridge die embedded in a core of the substrate which is at least partially under a first group of chiplets and a second group of chiplets, and wherein the plurality of interconnects is embedded in the bridge die. (Hughes, [0325]; regarding, “The bridge structure 2587 may be a dense interconnect structure that provides a route for electrical signals. The bridge structure 2587 may include a bridge substrate composed of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide a chip-to-chip connection between the logic or I/O chiplet 2574 and a memory chiplet 2575. The bridge structure 2587 may also be referred to as a silicon bridge or an interconnect bridge.”).
Regarding Claim 20 Hughes in view of Chen teaches the assembly of claim 16 as referenced above. Hughes in view of Chen further teaches:
wherein the one of more logics are an operating system that execute on the plurality of groups of chiplets. (Hughes, [0204]; regarding, “The programmable network interface 1210 can include a system on a chip (SoC 1220) that executes an operating system via multiple processor cores 1222.”).
Regarding Claim 21 Hughes in view of Chen teaches the assembly of claim 16 as referenced above. Hughes in view of Chen further teaches:
wherein the one or more logics, based on the first logic level of the indication, reconfigures the first and second sets of redundant interconnects to reclaim a logical configuration of the plurality of groups of chiplets, and wherein the logical configuration is one of a fully-connected configuration, a fat-tree configuration, or a mesh configuration. (Hughes, [0233]; regarding, “A ring or mesh based interconnect 1512 may be used to couple the internal components of the processor 1500. However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art...”).
Regarding Claim 22 Hughes in view of Chen teaches the assembly of claim 16 as referenced above. Hughes in view of Chen further teaches:
wherein the first logic level indicates presence of a fault in at least one of the first chiplet of the first group of chiplets and the first chiplet of the second group of chiplets, wherein the second logic level indicates absence of a fault in the plurality of groups of chiplets. (Chen, [0024]; regarding, “In operation… the data flit and ECC code are conveyed to the SR encode circuit 315A, which may implement circuitry similar to the multiplexer system circuitry of FIG. 2D, to configure the particular interconnect paths used for transmitting the flit and ECC signals.”; [0026]; regarding, “Once any defective contact paths are identified and bypassed using the redundant interconnects… the verified pathways are then stored… in the SR circuitry 315A itself, so that the updated paths may be used for normal communications operations.”; [0027]; regarding, “When in a normal operational mode, the flit data is conveyed through the SR encode circuitry (pathway network… Depending on whether defective units for the TxA_Flit and/or TxA_Ecc lines are identified or not, the TxA_RR lines will be, or will not be, used as needed.”).
Claims 12, 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hughes et al. (U.S. Publication No. 2025/0292349 A1), hereinafter referred to as Hughes, in view of Chen et al. (U.S. Publication No. 2025/0209027 A1), hereinafter referred to as Chen, in further view of Lissoos et al. (U.S. Publication No. 2025/0110740 A1), hereinafter referred to as Lissoos.
Regarding Claim 12, Hughes in view of Chen teach the apparatus of claim 1 as referenced above. Hughes in view of Chen fail to explicitly disclose but Lissoos teaches:
wherein the second encoding scheme is a one-hot encoding scheme. ([0036]; regarding, “The circuits of FIGS. 5A and 5B use a one-hot multiplexer select convention for the datapath multiplexers, in which a single select signal corresponding to an input to be selected is made to have a high value. In embodiments for which multiplexer selects are encoded using a different scheme, the circuits of FIGS. 5A and 5B can be used by first converting the select signals to one-hot format. The functionality of the circuits of FIGS. 5A and 5B can also be implemented using alternative logic suitable for other multiplexer select encoding schemes, as would be understood by one of ordinary skill in the art of digital circuit design.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Hughes and Chen with the teachings of Lissoos. Doing so could avoid unnecessary dynamic power consumption (Lissoos, [0018]).
Claims 15 and 19 are rejected under 35 U.S.C. 103 under the same grounds of rejection as claim 12.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Hughes et al. (U.S. Publication No. 2025/0292349 A1), hereinafter referred to as Hughes, in view of Chen et al. (U.S. Publication No. 2025/0209027 A1), hereinafter referred to as Chen, in further view of Shalf et al. (U.S. Publication No. 2014/0310467 A1), hereinafter referred to as Shalf.
Regarding Claim 23 Hughes in view of Chen teaches the assembly of claim 16 as referenced above. Hughes in view of Chen fail to explicitly disclose but Shalf teaches:
wherein the plurality of groups of chiplets are arranged in a torus configuration. ([0016]; regarding, “the processor cores 110 are connected in a mesh or grid topology. In another embodiment, the processor cores 110 are connected in a torus or ring topology. The processor cores 110 may be interconnected using other topologies, architectures, design schemes, paradigms, or in other ways.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Hughes and Chen with the teachings of Shalf. Doing so could improve energy efficiency (Shalf, [0024]).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Hughes et al. (U.S. Publication No. 2025/0292349 A1), hereinafter referred to as Hughes, in view of Chen et al. (U.S. Publication No. 2025/0209027 A1), hereinafter referred to as Chen, in further view of Govindachar et al. (U.S. Publication No. 2025/0190386 A1), hereinafter referred to as Govindachar.
Regarding Claim 24 Hughes in view of Chen teaches
A wafer-level assembly of chiplets comprising:
a plurality of groups of chiplets including a first group of chiplets, a second group of chiplets, (Hughes, [0319]; regarding, “A graphics processing unit, parallel processor, and/or compute accelerator as described herein can be composed from diverse silicon chiplets that are separately manufactured. In this context, a chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device. Additionally, the chiplets can be integrated into a base die or base chiplet using active interposer technology.”);
and a plurality of interconnects including a first set of interconnects and a second set of interconnects, wherein the first set of interconnects couples a first chiplet of the first group of chiplets with a first chiplet of the second group of chiplets, wherein the second set of interconnects couples a second chiplet of the first group of chiplets with a second chiplet of the second group of chiplets, (Hughes, [0320]; regarding, “a package assembly 2590 can include fewer or greater number of components and chiplets that are interconnected by an interconnect fabric 2585 or a bridge structure 2587. The bridge structure 2587 may be used to facilitate a point-to-point interconnect between, for example, a logic or I/O chiplet 2574 and memory chiplets 2575.”; [0321]; regarding, “The interconnect fabric 2585 may be an NoC interconnect or another form of packet switched fabric that switches data packets between components of the package assembly. For complex assemblies, the interconnect fabric 2585 may be a dedicated chiplet enables communication between the various hardware logic of the package assembly 2590.”);
wherein the plurality of interconnects is arranged in a mesh configuration, (Hughes, [0233]; regarding, “A ring or mesh based interconnect 1512 may be used to couple the internal components of the processor 1500.”);
wherein the first set of interconnects includes a first set of principle interconnects and a first set of redundant interconnects, wherein the second set of interconnects includes a second set of principle interconnects and a second set of redundant interconnects, (Chen, [0045]; regarding, “Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any compatible combination of, the examples described below.”; [0046]; regarding, “he first plurality of interconnect sections are part of a first integrated circuit (IC). The first plurality of interconnect sections are switchably coupled together through demultiplexer circuitry that has a first set of signal inputs, wherein the first plurality of interconnect sections include one or more redundant interconnect sections. The control circuitry controls the demultiplexer circuitry to redirect one or more of the signal inputs away from one or more faulty interconnect sections from the first plurality of interconnect sections to at least one of the one or more redundant interconnect sections. The first plurality of interconnect sections are to be coupled to complementary interconnect sections from a second IC.”);
wherein the plurality of interconnects is to transmit signals between the first chiplet of the first group of chiplets and the first chiplet of the second group of chiplets using one or more encoding schemes based on an indication from one or more logics associated with the plurality of groups of chiplets, (Chen, [0031]; regarding, “Multiprocessor system 400 is an interfaced system and includes a plurality of processors including a first processor 470 and a second processor 480 coupled via an interface 450 such as a point-to-point (P-P) interconnect, a fabric, and/or bus that may be implemented using spatially redundant interconnect systems”; [0024]; regarding, “In operation, a flit of data…to be transmitted to IC B is provided to the ECC generation circuit 310A, which processes the data bits… to generate an ECC code (TxA_Ecc) for the flit. From here, the data flit and ECC code are conveyed to the SR encode circuit 315A, which may implement circuitry similar to the multiplexer system circuitry of FIG. 2D, to configure the particular interconnect paths used for transmitting the flit and ECC signals.”);
wherein the one or more encoding schemes includes a first encoding scheme and a second encoding scheme, (Chen, [0019]; regarding, “…replacement scheme can fix a single failing region, i.e., a single unit for each class in a group, but if there are multiple fault regions that are spread out, another approach may be employed to complement the spatial redundancy scheme.”; [0022]; regarding, “Depending on the utilized scheme, for example, if separate multilane channels are used as is depicted, the complementary contact pairs may be divided in order to implement the separate multilane channels, or alternatively, separate interconnect tiles could be used for each multilane channel. As with many aspects of this disclosure, particular implementations will depend on specific design limitations and objectives.”);
wherein the first encoding scheme applies signals over some but not all of the first and second sets of redundant interconnects based on a first logic level of the indication, and wherein the second encoding scheme applies signals over the first and second sets of principle interconnects and the first and second sets of redundant interconnects based on a second logic level of the indication, (Chen, [0008]; regarding, “Disclosed are reliability solutions for multi-chip interconnect systems such as with HBI based interconnect schemes.”; [0019]; regarding, “The units from each class are coupled to an associated demultiplexer circuit 260, which has a set of 28 incoming signal inputs (e.g., data, ECC, or other), as shown, and channels the signal input pathways through selected units, bypassing any previously identified faulty unit, and directing the signal input paths out through multiplexer circuit 275. For example, the A chain, which includes units qA8, qA9, qA10, qA11, qA3, qaA2, qA1, and qA0 (redundant unit), is coupled to demultiplexer circuit 260A to receive signals A0-A27. Should any one of the units be faulty, the signal paths, beginning with the paths aligned with the faulty unit, are redirected, shifted rightward in this implementation, thereby effectively replacing the faulty unit with the redundant unit. For example, if the 4th unit (qA11) is bad, the signal paths A0-A11 are routed to the first three units (qA8-qA10), while signal paths A12-A27 are redirected through the last four units (qA3-qA0), thereby bypassing the faulty qA11 unit.”; [0065]; regarding, “A first portion of the complementary contact pairs are used as channels for the interconnect units, and a second portion of the complementary contact pairs are used to supply power from the first IC to the second IC. The plurality of interconnect units include a multiplicity of interconnect unit chains each including signal line and redundant interconnect units, wherein for each chain, a detected faulty one of the signal line interconnect units may be replaced in the chain with at least one of the redundant interconnect units.”);
and wherein the first logic level is different from the second logic level. (Chen, [0024]; regarding, “In operation… the data flit and ECC code are conveyed to the SR encode circuit 315A, which may implement circuitry similar to the multiplexer system circuitry of FIG. 2D, to configure the particular interconnect paths used for transmitting the flit and ECC signals.”; [0026]; regarding, “Once any defective contact paths are identified and bypassed using the redundant interconnects… the verified pathways are then stored… in the SR circuitry 315A itself, so that the updated paths may be used for normal communications operations.”; [0027]; regarding, “When in a normal operational mode, the flit data is conveyed through the SR encode circuitry (pathway network… Depending on whether defective units for the TxA_Flit and/or TxA_Ecc lines are identified or not, the TxA_RR lines will be, or will not be, used as needed.”).
Hughes in view of Chen fail to explicitly disclose but Govindachar teaches:
wherein the first group of chiplets is organized as a first fat-tree configuration, and wherein the second group of chiplets is organized as a second fat-tree configuration; ([0046]; regarding, “Digital Signal Processors (DSPs) 225, arranged on a chip 200 or chiplet, interface with virtual channels of a High Bandwidth Memory (HBM) 260 through the initiator fat-tree topology 230 and target fat-tree topology 240 of the network on chip 210.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Kumar with the teachings of Chopra. Doing so could reduce CPU overhead and enhance overall processing speed (Govindachar, [0050]).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Hughes et al. (U.S. Publication No. 2025/0292349 A1), hereinafter referred to as Hughes, in view of Chen et al. (U.S. Publication No. 2025/0209027 A1), hereinafter referred to as Chen, in further view of Govindachar et al. (U.S. Publication No. 2025/0190386 A1), hereinafter referred to as Govindachar, in further view of Lissoos et al. (U.S. Publication No. 2025/0110740 A1), hereinafter referred to as Lissoos.
Regarding Claim 25, Hughes in view of Chen in further view of Govindachar teach the assembly of claim 24 as referenced above. Hughes in view of Chen in further view of Govindachar fail to explicitly disclose but Lissoos teaches:
wherein the second encoding scheme is a one-hot encoding scheme. ([0036]; regarding, “The circuits of FIGS. 5A and 5B use a one-hot multiplexer select convention for the datapath multiplexers, in which a single select signal corresponding to an input to be selected is made to have a high value. In embodiments for which multiplexer selects are encoded using a different scheme, the circuits of FIGS. 5A and 5B can be used by first converting the select signals to one-hot format. The functionality of the circuits of FIGS. 5A and 5B can also be implemented using alternative logic suitable for other multiplexer select encoding schemes, as would be understood by one of ordinary skill in the art of digital circuit design.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Hughes and Chen and Govindachar with the teachings of Lissoos. Doing so could avoid unnecessary dynamic power consumption (Lissoos, [0018]).
Response to Arguments
Applicant’s arguments filed 04/29/2026 have been fully considered but are not persuasive.
Applicant argues Hughes in view of Chen fails to explicitly disclose two distinct encoding schemes selected by logic level indication (“Remarks”, Page 2). Examiner respectfully disagrees. As claimed, the limitation of Claim 1 recites “the one or more encoding schemes includes a first encoding scheme and a second encoding scheme” Under broadest reasonable interpretation of this limitation, the first and second encoding schemes can be the same encoding scheme. Further, Chen teaches “the A chain… is coupled to demultiplexer circuit 260A to receive signals A0-A27. Should any one of the units be faulty, the signal paths, beginning with the paths aligned with the faulty unit, are redirected… This replacement scheme can fix a single failing region… if there are multiple fault regions that are spread out, another approach may be employed to complement the spatial redundancy scheme” [0019]. Hughes in view of Chen teaches two distinct encoding schemes selected by logic level indication.
Applicant argues the cited arts’ redundant interconnects are only engaged upon fault detection, the opposite of the claimed second encoding scheme (“Remarks”, Page 3). Examiner respectfully disagrees. As claimed, the limitation of Claim 1 recites “the second encoding scheme applies signals over the plurality of principle interconnects and the plurality of redundant interconnects…” Based off the examiner’s response to the argument above and the interpretation of this limitation of claim 1, Hughes in view of Chen teaches the second encoding scheme applies signals over the plurality of principle interconnects and the plurality of redundant interconnects. The claim language does not commensurate with applicant’s arguments.
Applicant argues the cited art fails to disclose a first encoding scheme using “some but not all” redundant interconnects. (“Remarks”, Page 4). Examiner respectfully disagrees. As referenced in the above rejection Chen teaches “Each class chain includes like-class units 235 from clusters 8-11 and 0-3, with the units from cluster 0 providing the redundant units. The units from each class are coupled to an associated demultiplexer circuit 260, which has a set of 28 incoming signal inputs (e.g., data, ECC, or other), as shown, and channels the signal input pathways through selected units…” [0019]. Chen teaches a first encoding scheme using some but not all redundant interconnects.
Applicant argues Hughes in view of Chen fails to teach or suggest the inventive concept. (“Remarks”, Page 4). Examiner respectfully disagrees. Hughes in combination with Chen teaches the claimed invention as referenced in the above rejection. Further, Hughes and Chen are both considered to be analogous to the claimed invention because they are in the same field of processor redundancy and more specifically efficient redundancy when a fault occurs. combining Hughes with the teachings of Chen could limit the amount of overhead when replacing faulty interconnects and reduce additional faults (Chen, [0008]).
Applicant argues Hughes in view of Chen fails to disclose the specific two-level hierarchical organization of chiplets recited in Claim 16 (“Remarks”, Page 5). Examiner respectfully disagrees. For further clarification, Hughes discloses Fig. 8 and “Fig. 29… The multi-die GPU 2902 includes multiple chiplets 2802A-2802D, each of which includes at least one instance of a memory controller 2904, a shared cache 2906, compute cores 2908, and a set of die-to-die interconnects 2910A-2910B that couple with multiple adjacent chiplets… The die-to-die interconnects 2910A-2910B within each chiplets 2802A-2802D are configurable to operate in connected, disconnected, or limited connection modes to other chiplets [0338].” The clarifying citation and the previously cited paragraphs of Hughes teaches Claim 16. The claim language does not commensurate with applicant’s arguments.
Applicant argues Hughes in view of Chen in further view of Govindachar fails to disclose a chiplet group organization in a wafer-level assembly (“Remarks”, Pages 5-6). Examiner respectfully disagrees. Hughes teaches “In various embodiments a package assembly 2590 can include fewer or greater number of components and chiplets that are interconnected by an interconnect fabric 2585 or a bridge structure 2587. The bridge structure 2587 may be used to facilitate a point-to-point interconnect between, for example, a logic or I/O chiplet 2574 and memory chiplets 2575. In some implementations, the bridge structure 2587 may also be embedded within the substrate 2580. The chiplets within the package assembly 2590 may have a 2.5D arrangement using Chip-on-Wafer-on-Substrate (CoWoS) stacking in which multiple dies are stacked side-by-side on a silicon interposer that includes through-silicon vias (TSVs) to couple the chiplets with the substrate 2580, which includes electrical connections to the package interconnect 2583 [0320].” Hughes in combination with Chen and Govindachar teaches Claim 24.
Applicant argues Hughes in view of Chen in further view of Lissoos fails to disclose the application of one-hot encoding (“Remarks”, Page 6). Examiner respectfully disagrees. As previously discusses, Hughes in view of Chen teaches the claimed encoding schemes applied over interconnects. Lissoos teaches “The circuits of FIGS. 5A and 5B use a one-hot multiplexer select convention for the datapath multiplexers… In embodiments for which multiplexer selects are encoded using a different scheme, the circuits of FIGS. 5A and 5B can be used by first converting the select signals to one-hot format. The functionality of the circuits of FIGS. 5A and 5B can also be implemented using alternative logic suitable for other multiplexer select encoding schemes, as would be understood by one of ordinary skill in the art of digital circuit design” [0036]. Therefore, Hughes in combination with Chen and Lissoos teaches the claimed one-hot encoding scheme.
Applicant’s arguments regarding Claims 23 and 25 are not persuasive. Please see the addressed arguments referenced above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATHEW GUSTAFSON whose telephone number is (571)272-5273. The examiner can normally be reached Monday-Friday 8:00-4:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at (571) 272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL MASKULINSKI/Primary Examiner, Art Unit 2113
/M.D.G./Examiner, Art Unit 2113
Prosecution Insights