DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 20 is rejected under 35 U.S.C. 101 because claim 20 recites a computer-readable medium. The broadest reasonable interpretation of a claim drawn to a computer readable medium (also called machine readable medium and other such variations) typically covers forms of non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of computer readable media, particularly when the specification is silent. See MPEP 2111.01. When the broadest reasonable interpretation of a claim covers a signal per se, the claim must be rejected under 35 U.S.C. 101 as covering non-statutory subject matter. The USPTO recognizes that applicants may have claims directed to computer readable media that cover signals per se, which the USPTO must reject under 35 U.S.C. 101 as covering both non-statutory subject matter and statutory subject matter. A claim drawn to such a computer readable medium that covers both transitory and non-transitory embodiments may be amended to narrow the claim to cover only statutory embodiments to avoid a rejection under 35 U.S.C. 101 by adding the limitation "non-transitory" to the claim. Such an amendment would typically not raise the issue of new matter, even when the specification is silent because the broadest reasonable interpretation relies on the ordinary and customary meaning that includes signals per se.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, 11-14 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SEETHARAMAIA H (No. US-9087410-B2 “Seeth”).
Regarding claim 1, Seeth teaches “An apparatus for graphics processing, comprising:” (relate to an apparatus; Col 1, Line 39-40); (rendering graphics data; Col 1, Like 20-21);
“a memory; and” (graphics processing unit (GPU) architectures may require ... system memory when rendering a frame of graphics data; Col 2, Line 44-47);
“a processor coupled to the memory and, based on information stored in the memory, the processor is configured to:” (one or more processors to retrieve instructions, code and/or data structures for implementation of the techniques; Col 20, Line 31-33);
“determine, in a visibility-pass of image data for a set of bins, an indication of bin coverage for each bin in the set of bins; and” (may also generate a visibility stream during the binning pass, which may be separated according to bin; Col 8, Line 69-61); (generate visibility streams to indicate which primitives are visible in each bin; Col 17, Line 44-45); (the number of primitives in each of the bins, the number of visible primitives in each of the bins; Col 17, Line 49-51);
“render a portion of the image data associated with a bin in the set of bins based on the indication of bin coverage for the bin and a coverage threshold.” (render portions of an image that may benefit from the visibility information; Col 4, Line 40-42); (compare a received visibility score to a threshold; Col 19, Line 35-36); (if a visibility score is above a predetermined threshold (e.g., indicating high complexity and/or a large amount of overdraw), GPU driver 50 may designate the bin to be tile-based rendered. In contrast, if the visibility score is below the threshold (e.g., indicating few primitives and/or little overdraw), GPU driver 50 may designate the bin to be directly rendered; Col 19, Line 61-67);
Seeth discloses a visibility stream that indicates visibility in each bin that teach the claimed subject matter of bin coverage for each bin. Seeth also discloses rendering a portion of an image based on visibility information. This visibility information includes the visibility score compared to a threshold. This showcases bin coverage based on visibility, thus teaching the claimed subject matter.
Regarding claim 2, Seeth teaches “The apparatus of claim 1, wherein to render the portion of the image data, the processor is configured to:
render, in a render-pass and to a system memory that is separate from a graphics memory, the portion of the image data based on a determination that the indication of bin coverage for the bin fails to meet the coverage threshold.” (GPU 36 may directly render data by storing pixel values to display buffer unit 44 (or storage unit 48) following rendering, rather than storing the pixel values to GPU memory 38; Col 9, Line 19-21); (if the visibility score is below the threshold (e.g., indicating few primitives and/or little overdraw), GPU driver 50 may designate the bin to be directly rendered; Col 19, Line 65-67);
Seeth discloses rendering directly which directly rendering is to the system memory rather than the graphics memory. In addition, if the visibility score is below the threshold, it is directly rendered. This teaches the claimed subject matter of a render pass to a system memory based on bin coverage that fails to meet the threshold.
Regarding claim 3, Seeth teaches “The apparatus of claim 2, wherein to render the portion of the image data, the processor is configured to:
execute, prior to the render, a draw operation associated with the bin to generate draw data for the render;” (GPU driver 50 may designate areas of an image having a relatively large amount of overdraw for tile-based rendering. .... GPU driver 50 may also designate areas having a relatively small amount of overdraw for direct rendering; Col 19, Line 38-49);
“determine to refrain from performing a load operation to the graphics memory for the portion of the image data associated with the bin; and” (direct rendering does not require an entire chunk to be loaded to on-chip memory prior to rendering and transferred from on-chip memory to system memory after rendering; Col 3, Line 46-49); (on-chip graphics memory; Col 2, Line 53); (each chunk is loaded into local, on-chip GPU memory (load), rendered (render), and stored to system memory (store); Col 3, Line 37-39);
“determine to refrain from performing a store operation to the system memory for the portion of the image data associated with the bin.” (direct rendering does not require an entire chunk to be loaded to on-chip memory prior to rendering and transferred from on-chip memory to system memory after rendering; Col 3, Line 46-49); (each chunk is loaded into local, on-chip GPU memory (load), rendered (render), and stored to system memory (store); Col 3, Line 37-39);
Seeth discloses loading, rendering and sorting the data chuck into either graphics or system memory. Seeth also discloses overdraw used for rendering, which teaches the claimed subject matter of a draw operation used to generate data for rendering.
Regarding claim 4, Seeth teaches “The apparatus of claim 1, wherein the processor is further configured to:
render, in a render-pass and to a graphics memory that is separate from a system memory, a second portion of the image data associated with a second bin in the set of bins, based on a determination that the indication of bin coverage for the second bin meets the coverage threshold.” (With tile-based rendering, as described above, each chunk is loaded into local, on-chip GPU memory (load); Col 3, Line 36-38); (if a visibility score is above a predetermined threshold (e.g., indicating high complexity and/or a large amount of overdraw), GPU driver 50 may designate the bin to be tile-based rendered; Col 19, Line 61-64);
Seeth discloses rendering which is tile based rendering to the graphics memory rather than the system memory. In addition, if the visibility score meets or is above the threshold, it is tile based rendered. This teaches the claimed subject matter of a render pass to a graphics memory based on bin coverage that meets the threshold.
Regarding claim 5, Seeth teaches “The apparatus of claim 4, wherein to render, to the graphics memory, the second portion of the image data, the processor is configured to:
load, to the graphics memory, the second portion of the image data;” (bin may be referred to as a chunk of data. With tile-based rendering, as described above, each chunk is loaded into local, on-chip GPU memory (load); Col 3, Line 36-38);
“execute, prior to the render, a draw operation associated with the second bin to generate draw data;” (a visibility stream may allow fewer primitives to be processed (by skipping invisible primitives); Col 3, Line 32-34); (is typically most beneficial in situations in which at least a portion of an image has a relatively large amount of overdraw; Col 3, Line 52-54);
“render the second portion of the image data based on the draw data to generate rendered image data; and” (the GPU must load each chunk, render the chunk, and store the chunk to memory; Col 3, Line 66-67);
“store, to the system memory, the rendered image data in the second bin.” (the GPU must load each chunk, render the chunk, and store the chunk to memory; Col 3, Line 66-67);
Seeth discloses loading, rendering and sorting the data chuck into either graphics or system memory. Seeth also discloses overdraw used for rendering, which teaches the claimed subject matter of a draw operation used to generate data for rendering.
Regarding claim 6, Seeth teaches “The apparatus of claim 4, wherein to render, to the graphics memory, the second portion of the image data, the processor is configured to render the second portion of the image data prior to the render, to the system memory, of the portion of the image data.” (direct rendering does not require an entire chunk to be loaded to on-chip memory prior to rendering; Col 3, Line 46-48); (GPU 36 may use tile-based rendering to render portions of an image that may benefit from the visibility information.... may use direct rendering to render portions of an image in which tile-based rendering would result in latencies associated with the transfer of data from local, on-chip memory to system memory; Col 9-10, Line 65-67 & 2-6);
Seeth discloses tile rendering based on visibility information into GPU which determine the first of second bin based on visibility score. The tile rendered second portion is render in to graphics memory while the low visibility score portion is directly rendered to system memory. This teaches the claimed subject matter of rendering the second portion to graphics memory prior to rendering the second portion to system memory.
Regarding claim 7, Seeth teaches “The apparatus of claim 1, wherein to render the portion of the image data, the processor is configured to:
render, as a final rendering in a final render-pass, the portion of the image data.” (render the image using a binning configuration, wherein the binning configuration is based on the visibility information; Col 1, Line 55-57); (GPU 36 may receive the second command stream and render the image based on the second command stream; Col 18, Line 3-4); (GPU driver 50 may designate the remaining portion of image 90 to be directly rendered; Col 16, Line 65-67);
Seeth discloses rendering an image using a binning configuration that includes visibility information. As well as a command stream that renders the image based on command stream and rendering a portion for the image in directly rendering. This teaches the final render pass executed the portion of the image.
Regarding claim 8, Seeth teaches “The apparatus of claim 7, wherein to render the portion of the image data, the processor is configured to:
render, as a part of the final render in the final render-pass and combined with the portion of the image data, a second portion of the image data associated with a second bin in the set of bins based on the indication of bin coverage for the second bin and the coverage threshold.” (The GPU may process the initial binning configuration and generate visibility information based on the initial binning configuration. The GPU may send the visibility information to the GPU driver, which may generate a revised binning configuration based on the visibility information; Col 4, Line 53-58); (compare a received visibility score to a threshold; Col 19, Line 35-36); (GPU 36 may use tile-based rendering to render portions of an image that may benefit from the visibility information; Col 9, Line 65-67);
Seeth discloses visibility that determines the rendering configuration and the score compared to a coverage threshold. In addition, have portions of the image based on visibility information, that is used to later render the final image. This teaches the claimed subject matter of rendering a final render pass and portion of image.
Regarding claim 9, Seeth teaches “The apparatus of claim 8, wherein to render, as the part of the final render in the final render-pass and combined with the portion of the image data, the second portion of the image data, the processor is configured to:
execute, prior to the final render, a total number of draw operations associated with the bin and the second bin to generate combined draw data;” (command stream reconfiguration unit 76 may use the heuristic data to merge visibility streams until a predetermined complexity metric is attained. .... merge portions of the initial configuration of bins (using the visibility streams) based on a restricted region growing algorithm; Col 13, Line 49-55);
“wherein the final render is based on the generated combined draw data.” (GPU 36 may be responsible for reconfiguring the initial command stream. As noted above, the reconfigured command stream may drop one or more bins from tile-based rendering passes associated with the initial command stream, or may include a new binning arrangement that includes new, different bins and/or designated areas for direct rendering; Col 14, Line 27-33);
Seeth discloses a merge of portions of the bins using visibility streams until a determined metric is attained, this teaches the claimed subject matter of a number of operations with combined draw data. Seeth also discloses revised and reconfigured data from command stream that allow for direct rendering. This teaches the claimed subject matter of combined draw data for final rendering.
Regarding claim 11, Seeth teaches “The apparatus of claim 9, wherein to render, as the part of the final render in the final render-pass and combined with the portion of the image data, the second portion of the image data, the processor is configured to determine to refrain from performing, for each of the bin and the second bin:
an individual bin load to a graphics memory, that is separate from a system memory, for the image data;” (bin may be referred to as a chunk of data. With tile-based rendering, as described above, each chunk is loaded into local, on-chip GPU memory (load); Col 3, Line 36-38); (direct rendering does not require an entire chunk to be loaded to on-chip memory prior to rendering and transferred from on-chip memory to system memory after rendering; Col 3, Line 46-49); (the GPU is generally locked into performing either tile-based rendering or direct rendering for an entire image; Col 4, Line7-8);
“a set of individual draws;” (allow fewer primitives to be processed (by skipping invisible primitives), there is a computational cost associated with rendering an image bin by bin. Each bin may be referred to as a chunk of data; Col 3, Line 33-36);
“an individual rendering; and” (bin may be referred to as a chunk of data. With tile-based rendering, as described above, each chunk is loaded into local, on-chip GPU memory (load), rendered (render), and stored to system memory (store); Col 3, Line 36-39);
“an individual store to the system memory for the image data.” (bin may be referred to as a chunk of data. With tile-based rendering, as described above, each chunk is loaded into local, on-chip GPU memory (load), rendered (render), and stored to system memory (store); Col 3, Line 36-39);
Seeth teaches tile rendering and direct rendering which is separate and allows for a bin to be loaded separate from the other rendering. Aswell as a chuck od data being a bin which relates to an individual load, rendering, and storing to system memory. This teaches the claimed subject matter of individual load, draws, rendering and storing of image data.
Regarding claim 12, Seeth teaches “The apparatus of claim 11, wherein to determine to refrain from performing, for each of the bin and the second bin, the processor is configured to determine to refrain from performing prior to the final render.” (The visibility stream may control the rendering pass (described below). For example, the visibility stream may be used to skip sequences of invisible primitives during rendering; Col 3, Line 11-14);
Seeth discloses control of the rendering which can be used to skip primitives during rendering. This control of the rendering and skipping showcases the refrain from preforming before the final rendering, thus teaching the claimed subject matter.
Regarding claim 13, Seeth teaches “The apparatus of claim 11, wherein to determine to refrain from performing, for each of the bin and the second bin, the processor is configured to determine to refrain from performing subsequent to at least one render, to the graphics memory, of the image data respectively associated with at least one bin of the set of bins, which excludes the bin and the second bin, wherein the at least one render is associated with respective indications of bin coverage for the at least one bin that meets the coverage threshold.” (the GPU is generally locked into performing either tile-based rendering or direct rendering for an entire image; Col 4, Line7-8); (GPU 36 and GPU driver 50 may perform direct rendering ....in some areas of an image, while performing tile-based .... in other areas of the same image; Col 9, Line 59-64); (if the visibility score is below the threshold ...GPU driver 50 may designate the bin to be directly rendered; Col 19, Line 65-67); (if a visibility score is above a predetermined threshold ... GPU driver 50 may designate the bin to be tile-based rendered; Col 19, Line 61-64);
Seeth discloses mixed rendering configuration in which some bins are tile rendered with graphics memory and others are directly rendered. With the rendering locked between tile based or direct rendering for an image, it teaches the claimed subject matter of refraining from preforming at least one render. As well as at least one bin meeting the threshold.
Regarding claim 14, Seeth teaches “The apparatus of claim 1, wherein to determine the indication of bin coverage for each bin in the set of bins, the processor is configured to perform at least one of:
calculate the bin coverage for each bin in the set of bins; or” (GPU 36 may use the visibility streams and/or heuristic data to assign a visibility score to each bin; Col 17, Line 52-54);
“adjust in a data structure, for each bin in the set of bins and based on the bin coverage for each bin, a respective indication of bin coverage that is associated with the coverage threshold.” (GPU 36 may use the visibility streams and/or heuristic data to assign a visibility score to each bin; Col 17, Line 52-54); (compare a received visibility score to a threshold; Col 19, Line 35-36);
Seeth discloses a visibility score that is based on the visibility stream or the heuristic data to get the score. The visibility score is the bin coverage of each bin and getting the score or heuristic data showcases the calculation of the bin coverage. Thus, teaching the claimed subject matter of calculating the bin coverage and adjusting the data to include the bin coverage associated with the threshold.
Regarding claim 17, Seeth teaches “The apparatus of claim 1, wherein to render the portion of the image data, the processor is configured to render, to a system memory, the portion of the image data, wherein the system memory is a video memory that is separate from a graphics memory dedicated to a graphics processing unit (GPU).”(GPU 36 may directly render data by storing pixel values to display buffer unit 44 (or storage unit 48) following rendering, rather than storing the pixel values to GPU memory 38; Col 9, Line 19-21);
Seeth discloses storing pixel values to display buffer rather than storing in n GPU memory. It is obvious to a person skilled in that art that storing pixel values to display is exactly what video memory (VRAM) does which teaches the claimed subject matter of system memory is a video memory rather than GPU memory.
Regarding claim 18, Seeth teaches “The apparatus of claim 1, wherein the apparatus is a wireless communication device.” (wireless devices, mobile or cellular telephones, including so-called smartphones, personal digital assistants (PDAs), video gaming consoles.... and the like; Col 5, Line 1-7);
Seeth discloses wireless devices like phones and the like, that can be used to communicate which teach the claimed subject matter of a wireless communication device.
Regarding claim 19, Seeth teaches “A method of graphics processing, comprising:” (relate to a method; Col 1, Line 33); (rendering graphics data; Col 1, Like 20-21);
Claim 19 is directed to a method and its limitations are similar in scope and functions performed by the apparatus of claim 1. Therefore, claim 19 limitations are also rejected with the same rationale as regarding claim 1.
Regarding claim 20, Seeth teaches “A computer-readable medium storing computer executable code, the computer executable code, when executed by a processor, causes the processor to:” (computer-readable storage medium having instructions stored thereon that, when executed, cause one or more processors; Col 1, Line 51-54); (rendering graphics data; Col 1, Like 20-21);
Claim 20 is directed to a computer-readable medium and its limitations are similar in scope and functions performed by the apparatus of claim 1. Therefore, claim 20 limitations are also rejected with the same rationale as regarding claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over SEETHARAMAIA H in view of GRUBER (No. US-9569811-B2 “Gruber”).
Regarding claim 10, while Seeth fails to teach the all of claim 10, Gruber teaches “The apparatus of claim 9, wherein the combined draw data comprises a combined visibility stream over the bin and the second bin; or” (A visibility stream may be generated for an entire image, or may be generated on a per-bin basis; Col 2, Line 66-67); (overlap unit 76 may mark a single pixel as being visible in more than one bin (e.g., more than one visibility stream); Col 14, Line 61-63);
wherein to render, as the part of the final render in the final render-pass and combined with the portion of the image data, the second portion of the image data, the processor is configured to render based on a combined bin scissor operation.” (GPU 36 may then determine scissor parameters that include the bin and the overlap region. GPU 36 may then render the pixels identified by the scissor region and store the rendered pixels to GPU memory 38. In this way, GPU 36 may render a series of overlapping bins; Col 16, Line 2-7);
Gruber discloses visibility spanning multiple bins and an overlap unit which is obvious teaches a combined visibility stream over the bins. Thus, teaches the claimed subject matter of a visibility steam over the bins. Also, Gruber discloses bin scissor-based rendering of the bin and overlap region which it would be obvious that scissor region covers both the bin and overlap which we could relate to the second bin, thus teaching the claimed subject matter.
Seeth and Gruber are analogous art as both of them are related to rendering graphics data and generating visibility information.
The motivation for the above is to have accurate combination of data for efficient final render pass.
Therefore, it would have been obvious for an ordinary skilled person in the art before the effective filing date of claimed invention to have modified Seeth by wherein the combined draw data comprises a combined visibility stream over the bin and the second bin; or wherein to render, as the part of the final render in the final render-pass and combined with the portion of the image data, the second portion of the image data, the processor is configured to render based on a combined bin scissor operation as taught by Gruber.
Regarding claim 15, while Seeth fails to teach the all of claim 15, Gruber teaches “The apparatus of claim 14, wherein to calculate the bin coverage for each bin in the set of bins, the processor is configured to calculate, via a rasterizer, the bin coverage for each bin in the set of bins;” (Visibility unit 72 may receive the rasterized data from rasterizer 68 and generate visibility information; Col 13, Line 9-10);
“wherein to adjust in the data structure, for each bin in the set of bins and based on the bin coverage for each bin, the respective indication of bin coverage, the processor is configured to adjust in the data structure, via a command processor, the respective indication of bin coverage.” (Command processor 60 may be responsible for reading a command stream from GPU driver 50; Col 11, Line 65-66); (GPU driver 50 may access the visibility information and generate command streams for rendering each bin; Col 9, Line 1-2);
Gruber discloses a visibility unit that gets rasterized data and generates visibility information from it, which teachers the bin coverage of each bin by calculation of a rasterizer. Gruber also discloses a command processor that receives command streams. The command steams access visibility information of the bin which relates to the bin coverage of the bin. It would be obvious for the command stream of the command processor to adjust the data structure. Therefore, teaches the claimed subject matter.
The motivation for the above is to have accurate calculation of bin coverage for more efficient rendering.
Therefore, it would have been obvious for an ordinary skilled person in the art before the effective filing date of claimed invention to have modified Seeth by wherein to calculate the bin coverage for each bin in the set of bins, the processor is configured to calculate, via a rasterizer, the bin coverage for each bin in the set of bins; wherein to adjust in the data structure, for each bin in the set of bins and based on the bin coverage for each bin, the respective indication of bin coverage, the processor is configured to adjust in the data structure, via a command processor, the respective indication of bin coverage as taught by Gruber.
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over SEETHARAMAIA H in view of ACHARYA (No. US-12086899-B2 “Acharya”).
Regarding claim 16, while Seeth fails to teach the all of claim 16, Acharya teaches “The apparatus of claim 1, wherein the processor is further configured to:
obtain the coverage threshold, wherein the coverage threshold is based on a configuration associated with a user-mode driver (UMD) or a kernel-mode driver (KMD) for a workload to which the image data corresponds.” (a driver, such as a user-mode driver (UMD) or kernel-mode driver (KMD), receives performance data, such as sensor data and performance counter data, and selects the binning mode based on the performance data; Col 3, 33-37);
(A given command buffer 114 includes commands one or multiple workloads, and each workload is configured to be executed in a two-level binning mode, a non-two-level binning mode, or is executable in either mode. Upon completing the recording of commands to the command buffer 114 by the UMD 110, a KMD 112 submits the command buffer 114 to the GPU; Col 4, Line 2-8);
Acharya discloses a user-mode driver (UMD) and/or a kernel-mode driver (KMD) used for performance data. They also disclose commands buffer that commands workloads for the binning of the image. This teaches the claimed subject matter of a user-mode driver (UMD) or a kernel-mode driver (KMD) for workload. In combination with what Seeth teaches about visibility score and the threshold of coverage, it would be obvious to a person skilled in the art.
Seeth and Acharya are analogous art as both of them are related to rendering graphics data and a graphics processing unit.
The motivation for the above is to efficient configuration from driver(s) for efficient workload.
Therefore, it would have been obvious for an ordinary skilled person in the art before the effective filing date of claimed invention to have modified Seeth by obtaining the coverage threshold, wherein the coverage threshold is based on a configuration associated with a user-mode driver (UMD) or a kernel-mode driver (KMD) for a workload to which the image data corresponds as taught by Acharya.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
EP-4220567-B1 (Howard) – Discloses a graphics processing unit is configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles.
US-11373268-B2 (Alla) – Discloses rendering of video/graphics content by a graphics processing unit. The apparatus can configure the graphics processing unit of a display apparatus to perform multiple rendering passes for a frame of a scene to be displayed on a display device.
US-20220036634-A1 (Varadarajan) – Discloses packing coverage in a graphics processing unit (GPU) may include receiving an indication for a portion of an image, determining, based on the indication, a packing technique for the portion of the image, and packing coverage for the portion of the image based on the packing technique.
US-20200211511-A1 (Schluessler) – Discloses data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.
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/B.D.P./Examiner, Art Unit 2612
/Said Broome/Supervisory Patent Examiner, Art Unit 2612
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